Section 4
Hardware Architecture
The SDRAM Initialization sequence summary is as follows:
;Load the UPM(A) data
1. Load the UPM(A) data --- see below for the UPM(A) data.
;Memory Bank 1 initialization
2. Init Option_REG_bank1---[OR1]
3. Init BASE_REG_bank1-----[BR1]
;SDRAM_INIT
4. INIT SDRAM mode register --- [MAR] = 0x88.
5. Run MRS command from UPM data 0x2B --- MCR = 0x8000212B
6. Set the UPMA_MODE_REG
7. Set the MCR for refresh --- MCR = 0x80002130 (0x30 of the UPM(A) data
has the refresh sequence)
8. Set the UPMA_MODE_REG
UPM_Initialize_Values:
; UPM A RAM Array
; Single Read (Offset 0x0)
.long 0xeffefc04, 0x0ffcfc04, 0xeeefb004, 0x00af3004
.long 0xeffaf000, 0x0ff0f004, 0xfffffc05, 0xfffffc04
; Burst Read (Offset 0x8)
.long 0xeffefc04, 0x0ffcfc04, 0xeeefb004, 0x00af3004
.long 0xf0fff000, 0xf0fff000, 0xe0faf000, 0x0ff0f000
.long 0xfffff005, 0xfffffc04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
; Single Write (Offset 0x18)
.long 0xeffefc04, 0x0ffcfc04, 0xeeebb000, 0x00a33004
.long 0xeffaf004, 0x0ff0f004, 0xfffffc05, 0xfffffc04
; Burst Write (Offset 0x20)
.long 0xeffefc04, 0x0ffcfc04, 0xeeebb000, 0x00a33000
.long 0xf0fff000, 0xf0fff000, 0xe0faf004, 0x0ff0f004
.long 0xfffffc05, 0xfffffc04, 0xfffffc04, 0xefdafc34
.long 0x0fe0fc34, 0xefaab034, 0x1fb57435, 0xfffffc04
; Refresh (Offset 0x30)
.long 0xeffebc04, 0x0ffc3c04, 0xfffffc04, 0xfffffc04
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc05
.long 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04
; Exception (Offset 0x3c)
.long 0xeffffc04, 0x0ffffc04, 0xfffffc05, 0xfffffc04
4-6
PCI 9054RDK-860 Hardware Reference Manual v2.3
© 2005 PLX Technology, Inc. All rights reserved.
