Section 4
Hardware Architecture
The MPC860 power-on configuration is done while HRESET# is asserted. MODCK[1:2] determines the
initial operating frequency, while U34 and the pull up/down resistor network determines the other
MPC860 initial operating mode. Any of these power-on configuration settings can be reprogrammed by
way of the software after boot up.
Either a 4-MHz or a 50-MHz oscillator is used to generate a reference clock to the MPC860. The MPC860
generates Local Bus Clock Out (CLKOUT) to the clock buffer. In turn, the clock buffer generates all Local
Bus clocks, including the PCI 9054 (LCLK), SDRAM (SDRAM_CLK), and PLX Option Module 2
(POM2_CLK) clocks.
Note: Refer to the section, “
,” for further design notes.
All MPC860 peripheral signals are connected to the POM2 (PLX Option Module 2) for MPC860 peripheral
expansion. Only SSC1 is used as the PLXROM debug connection to the remote terminal. All other
peripheral expansion is available to the user.
The GPL(A) ports and BS_A port are used to control the SDRAM. The GPL(A)[0:3] signals are connected
to all SDRAM control signals, as well as the external address Mux (U31, U32, and U33). BS_A[0:3] are
used as a Read/Write Enable signal. Refer to the section, “SDRAM,” for more information.
One of the MPC860 internal Chip Selects (CS[3:0]#) is used to access the PCI 9054 internal registers
(CS3# or CS9054#). CS0# is assigned to access the FLASH (CSFLASH#), while CS1# is used to access
the SDRAM (CSSDRAM#).
For exception process, IRQ1# is connected to the PCI 9054 Local Interrupt In/Out pin in addition to the
TEA# and the RETRY# signals from the PCI 9054.
4.4 Clock
The MPC860 accepts the 4 MHz external clock (MODCK[1:2] = 'b11) or 50 MHz external clock
(MODCK[1:2] = 'b10), and generates the CLKOUT to clock buffer (U9, CY2305). The CLKOUT frequency
is programmable via MPC860 internal clock circuit—4 MHz times 12 (48 MHz), 13 (52 MHz), 50 MHz
times 1, or other combinations.
The MPC860 and PCI 9054 are rated at 50 MHz. In turn, the clock buffer generates LCLK to the PCI
9054, POM2_CLK to the POM2 connector, and SDRAM_CLK to the SDRAM. In addition, there is a
SPARE_CLK, with a capacitor termination of 10 pF. All clock outputs from U9 (CY2305) should have the
same loading to maintain zero delay between input clock (MPC860 CLKOUT) and all outputs.
The phase of the outputs can be adjusted by way of C38, a terminating capacitor on the SPARE_CLK
signal. If C38 is larger than the loading of each clock (LCLK, SDRAM_CLK, and POM2_CLK), then the
phase shift is negative (
that is
, output leads input). If C38 is smaller than the loading of each clock, the
phase shift is positive (
that is
, output lags input). Each clock loading should be 10 to 15 pF (plus trace
capacitance).
Note: Refer to the section, “Schematics
,”
for the clock circuits and optional clock termination circuits.
4.4.1 PCI
Clock
The PCI Bus Clock (PCLK) supports speeds up to 33 MHz.
4.4.2 Local
Clock
The Local Bus Clock (CLKOUT) can be any multiple of 4 MHz, programmable with the MPC860 internal
clock generator or 50 MHz with the 50 MHz external oscillator. The PCI 9054RDK-860 is built and set to
50 MHz with an external 50 MHz oscillator.
Note
: The PCI 9054 and the MPC860 are limited to 50 MHz.
PCI 9054RDK-860 Hardware Reference Manual v2.3
© 2005 PLX Technology, Inc. All rights reserved.
4-3
