VSX-AX4AVi-S
258
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4
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C
D
F
A
B
E
No. Pin Name
I/O
Function
No. Pin Name
I/O
Function
1
HSYNC
I
Horizontal sync input control signal
41
CI2CA
I
I2C device address select
2
VSYNC
I
Vertical sync input control signal
42
RESET#
I
Reset pin (Active Low.)
3
CGND
−
Digital core GND
43
CSCL
I
I2C clock
4
CVCC18
−
Digital core VCC (1.8V)
44
CSDA
Bi-Di I2C data (Open drain output)
5
SPDIF
I
S/PDIF audio input
45
CVCC18
−
Digital core VCC (1.8V)
6
MCLK
I
Audio input master clock
46
CGND
−
Digital core GND
7
SD3
I
I2S serial data
47
IOGND
−
IO pin GND
8
SD2
I
I2S serial data
48
IOVCC
−
IO pin VCC (3.3V)
9
SD1
I
I2S serial data
49
D23
I
12-bit input pixel data bus
10
SD0
I
I2S serial data
50
D22
I
12-bit input pixel data bus
11
WS
I
I2S word select
51
D21
I
12-bit input pixel data bus
12
SCK
I
I2S serial clock
52
D20
I
12-bit input pixel data bus
13
IOVCC
−
IO pin VCC (3.3V)
53
D19
I
12-bit input pixel data bus
14
IOGND
−
IO pin GND
54
D18
I
12-bit input pixel data bus
15
CGND
−
Digital core GND
55
D17
I
12-bit input pixel data bus
16
CVCC18
−
Digital core VCC (1.8V)
56
D16
I
12-bit input pixel data bus
17
INT
O
Interrupt output
57
D15
I
12-bit input pixel data bus
18
HPD
I
Hot plug detect input
58
D14
I
12-bit input pixel data bus
19
DSDA
Bi-Di DDC data (Open drain output)
59
CVCC18
−
Digital core VCC (1.8V)
20
DSCL
Bi-Di DDC clock
60
CGND
−
Digital core GND
21
RSVDL
I
Reserved for use by sillicon image, and
must be tied Low.
61
D13
I
12-bit input pixel data bus
22
PGND1
−
TMDS core PLL ground
62
D12
I
12-bit input pixel data bus
23
PVCC1
−
TMDS core PLL power (3.3V)
63
D11
I
12-bit input pixel data bus
24
EXT_SWING
I
Voltage swing adjust
64
D10
I
12-bit input pixel data bus
25
AGND
−
Analog GND
65
D9
I
12-bit input pixel data bus
26
TXC-
O
TMDS output clock pairs
66
IDCK
I
Input data clock
27
TXC+
O
TMDS output clock pairs
67
D8
I
12-bit input pixel data bus
28
AVCC
−
Analog VCC (3.3V)
68
D7
I
12-bit input pixel data bus
29
TX0-
O
TMDS output data pairs
69
D6
I
12-bit input pixel data bus
30
TX0+
O
TMDS output data pairs
70
D5
I
12-bit input pixel data bus
31
AGND
−
Analog GND
71
IOVCC
−
IO pin VCC (3.3V)
32
TX1-
O
TMDS output data pairs
72
IOGND
−
IO pin GND
33
TX1+
O
TMDS output data pairs
73
CGND
−
Digital core GND
34
AVCC
−
Analog VCC (3.3V)
74
CVCC18
−
Digital core VCC (1.8V)
35
TX2-
O
TMDS output data pairs
75
D4
I
12-bit input pixel data bus
36
TX2+
O
TMDS output data pairs
76
D3
I
12-bit input pixel data bus
37
AGND
−
Analog GND
77
D2
I
12-bit input pixel data bus
38
PVCC2
−
Filter PLL power (3.3V)
78
D1
I
12-bit input pixel data bus
39
PGND2
−
Filter PLL ground
79
D0
I
12-bit input pixel data bus
40
NC
−
Not connected
80
DE
I
Data enable
Pin Function
