VSX-AX4AVi-S
257
5
6
7
8
5
6
7
8
C
D
F
A
B
E
SiI9030CTU (HDMI & DVC ASSY : IC301)
• HDMI PanelLink Transmitter
Pin Arrangement (Top view)
CI2CA
41
RESET#
42
CSCL
43
CSDA
44
CVCC18
45
CGND
46
IOGND
47
IOVCC
48
D23
49
D22
50
D21
51
D20
52
D19
53
D18
54
D17
55
D16
56
D15
57
D14
58
CVCC18
59
CGND
60
D13
61
D12
62
D11
63
D10
64
D9
65
IDCK
66
D8
67
D7
68
D6
69
D5
70
IOVCC
71
IOGND
72
CGND
73
CVCC18
74
D4
75
D3
76
D2
77
D1
78
D0
79
DE
80
NC
40
PGND2
39
PVCC2
38
AGND
37
TX2+
36
TX2-
35
AVCC
34
TX1+
33
TX1-
32
AGND
31
TX0+
30
TX0-
29
AVCC
28
TXC+
27
TXC-
26
AGND
25
EXT_SWING
24
PVCC1
23
PGND1
22
RSVDL
21
DSCL
20
DSDA
19
HPD
18
INT
17
CVCC18
16
CGND
15
IOGND
14
IOVCC
13
SCK
12
WS
11
SD0
10
SD1
9
SD2
8
SD3
7
MCLK
6
SPDIF
5
CVCC18
4
CGND
3
VSYNC
2
HSYNC
1
DSCL
20
DSDA
44
Block Diagram
IDCK
66
INT
17
HPD
18
EXT_SWING
24
TXC
±
TX0
±
TX1
±
TX2
±
CSCL
43
CI2CA
41
RESET#
42
D[23:0]
HSYNC
1
VSYNC
2
DE
80
Video Data
Capture/
DE Gen./
656 Logic
Block
SPDIF
5
MCLK
6
SCK
12
WS
11
SD[3:0]
Audio Data
Capture
Logic
Block
Control Signals
Audio Data
Encrypted
Data
PanelLink
TMDS
Digital
Core
TM
CSDA
44
Registers
-------------
Configuration
Logic Block
I2C
Slave
49-58,61-65,
67-70,75-79
26,27
29,30
32,33
35,36
7-9
4:2:2 to
4:4:4
E-DDC
Master
Receiver Sense + Interrupt Logic
HDCP
Keys
EEPROM
HDCP
Encryption
Engine
CSC
XOR