107
MEP-7000
5
6
7
8
5
6
7
8
A
B
C
D
E
F
D201
LV
StatusLED
Device
dia
g
nosis
Defective device
Remarks
How to check
Jud
g
ment
Main CPU
(SOUTH CPU),
flash ROM, or SDRAM
• Defective CPU
• Defective bus (Because of equal-length
wiring, even if one of the cables is defective,
a device connected to that bus becomes
unstable.)
*In a case of a failure in the line from the
CPU to the SDRAM CS, operation of the
LEDs is irregular.
S3
AUDIO DSP
N
G
Audio DSP
Configuration of the AUDIO-DSP is not
completed.
S0
×
(Unlit)
(Flashes 3 times)
S4
FPGA
N
G
(Flashes 4 times)
(Flashes 5 times)
S5
USB
CO
N
TROLLER
N
G
FPGA
Configuration of the FPGA is not completed.
*
N
ote that communication with the main CPU
(SOUTH CPU) is normal even if the 16-MHz
clock (for audio sync) is defective.
*If the FPRGM line is defective.
(Communication
between units)
SERVO
DRIVE 2
N
G
Servo drive 2
USB controller
Configuration of the USB controller is not
completed.
ATAPI 1 communication is not possible with
the drive 2 optical disc controller.
SERVO
DRIVE 1
N
G
S
8
(Flashing continuously)
(Flashes 6 times)
(Flashes 7 times)
S7
S6
SUD2
(Lit)
N
ormal startup
SUD1
(Flashing asynchronously)
Transmission of updater files to the control
unit (
N
ORTH CPU) is in progress.
*Currently, the Firmware Updating Program
(DJS) method is not supported.
×
(Lit for 2 sec)
SOK
W
riting of updater-file data to the flash
memories of the drive unit (SOUTH CPU/
Servo 1/Servo 2) is in progress.
*Currently, the Firmware Updating Program
(DJS) method is not supported.
(During updating)
Communication with the control unit
(
N
ORTH Unit) is not possible.
Servo drive 1
ATAPI 1 communication is not possible with
the drive 1 optical disc controller.
Memo
: If several devices are in failure, the least critical failure is indicated with the LEDs.
Memo
: If the S5 step is successfully cleared, the startup sequence will not be interrupted even if not all devices
operate
properly.
Memo
: It may take dozens of seconds for the unit to determine OK or
N
G for devices other than the AUDIO
DSP/FPGA, because of retries.