199
MEP-7000
5
6
7
8
5
6
7
8
A
B
C
D
E
F
FPGA confi
g
uration_1
FPGA confi
g
uration_2
DAC RESET
7
8
9
N
o.(SCH/PCB)
CH1
FPRGM
19
FPRGM (TP)
CH2
FDO
N
E
20
FDO
N
E (TP)
CH3
SPICLK
5
SPICLK (TP)
CH4
SPIOUT
7
SPIOUT (TP)
CH1
CH2
CH3
CH4
a-b 325ms
N
o.(SCH/PCB)
CH1
FPRGM
19
FPRGM (TP)
CH2
FPGARST#
1
8
FPGARST# (TP)
CH3
FDO
N
E
20
FDO
N
E (TP)
CH4
SPICLK
5
SPICLK (TP)
CH1
CH2
CH3
CH4
a-b 325ms
N
o.(SCH/PCB)
CH1
RST#
2
RST# (TP)
CH2
DAC_16M
10
DAC_16M (TP)
CH3
DACRST#
12
DACRST# (TP)
CH1
CH2
CH3
a-b = 1555.00ms
5.0V/div
5.0V/div
2.0V/div
2.0V/div
500ms/div
5.0V/div
5.0V/div
5.0V/div
5.0V/div
10ms/div
5.0V/div
5.0V/div
10ms/div
2.0V/div
CH2
DAC_16M
CH3
DAC_RST#
a
b
CH1
RST#
CH1
FPRGM
CH2
FDO
N
E
CH3
SPICLK
CH4
SPIOUT
CH1
FPRGM
CH2
FPGARST#
CH3
FDO
N
E
CH4
SPICLK
a
b
a
b
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
Completion of FPGA configuration
Start of FPGA configuration
Completion of FPGA configuration
Start of FPGA configuration
DAC Reset Clear
South CPU Reset Clear
Measurement conditions
At the time of power on
Voltage
Time
Signal
N
ame
Measurement Point
Measurement conditions
At the time of power on
Voltage
Time
Signal
N
ame
Measurement Point
Measurement conditions
At the time of power on
Voltage
Time
Signal
N
ame
Measurement Point