DEQ-P8000/UC
40
1
2
3
4
1
2
3
4
C
D
F
A
B
E
61
62
63
64
65
AKDRDY
66
67
32KSW
68
AKCKS1
69
aksrst
70
akirst
71
akrq
72
yssr1
73
yssic
74
ysscs
75
CKSO
76
77
NC
78
VREF
79
AVCC
AVSS
80
YSSRX
YSSTX
I
O
O
I
I
I
O
O
O
I
O
O
O
O
O
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
DSPPW
ysslock
DSP : Power supply output
AK7730 : DRDY detection terminal
AK7730 : RDY detection terminal
AKMCK switch (fs32K) H : 32kHz L : Others
AK7730 : Master clock selection pin 1
AK7730 : System reset pin
AK7730 : Initial reset pin
AK7730 : Request pin
YSS : PLL initialization signal output terminal
YSS : Reset terminal
YSS : Chip select
AK7730 : Clock switch
Analog GND
Not used
A/D : Reference voltage
Analog power supply
YSS : Communication data input
YSS : Communication data output
YSS : PLL lock detection terminal
DAC : Communication data input
DACRX
AKRDY
* PD5967A
60
61
80
1
40
41
21
20
Pin No.
Pin Name
I/O
Format
Function and Operation
Format
Meaning
C
CMOS
N
N channel open drain
1
2
3
V
IN
GND
V
c
5
Controller
4
V
o
N
R
PQ1X331M2ZP
PQ1X251M2ZP
Controller
Vin
GND
Vc
Vo
Nr
1
2
3
5
4
Summary of Contents for DEQ-P6600/EW
Page 4: ...DEQ P8000 UC 4 1 2 3 4 1 2 3 4 C D F A B E 1 SPECIFICATIONS ...
Page 5: ...DEQ P8000 UC 5 5 6 7 8 5 6 7 8 C D F A B E ...
Page 6: ...DEQ P8000 UC 6 1 2 3 4 1 2 3 4 C D F A B E ...
Page 7: ...DEQ P8000 UC 7 5 6 7 8 5 6 7 8 C D F A B E ...
Page 10: ...DEQ P8000 UC 10 1 2 3 4 1 2 3 4 C D F A B E 2 2 EXTERIOR ...
Page 22: ...DEQ P8000 UC 22 1 2 3 4 1 2 3 4 C D F A B E A A AUDIO CONTROL UNIT IC Q ...
Page 23: ...DEQ P8000 UC 23 5 6 7 8 5 6 7 8 C D F A B E A SIDE B ...