32
TSP-16
1
2
3
4
A
B
C
D
E
F
1
2
3
4
IN/OUT
Pull-up Setting
Pin No.
Select Function
Signal Name
Description
Normal
Operation
During
Reset
Internal
External
W4 gpio4.GPIO4_IO11
NC
UNU
S
ED O
(L)
Input
PU
(100K)
U5
i2c2.I2C2_
S
CL iMX_PMIC/AUTH_
S
CL
PMIC CONTROL
(Authentication IC Control : UNU
S
ED)
O Input PU
(100K)
PU4.7k
T7
i2c2.I2C2_
S
DA iMX_PMIC/AUTH_
S
DA
PMIC CONTROL
(Authentication IC Control : UNU
S
ED)
IO Input PU
(100K)
PU4.7k
T6
gpio4.GPIO4_IO14 U
S
BPWR_OC
U
S
B-A POWER
S
UPPLY CURRENT MONITORING
L : Overcurrent H : Normal
I Input
PU
(100K)
V5
usb.U
S
B_OTG_PWR U
S
BPWR_EN
U
S
B-A POWER
S
UPPLY CONTROL
L : OFF H : ON
O Input PD
(100K)
B11 MLB_CLK_P
NC
(MLB)
UNU
S
ED (MLB port)
—
—
A11 MLB_CLK_N
NC
(MLB)
UNU
S
ED (MLB port)
—
—
B9 MLB_
S
IG_P NC
(MLB)
UNU
S
ED (MLB port)
—
—
A9 MLB_
S
IG_N NC
(MLB)
UNU
S
ED (MLB port)
—
—
A10 MLB_DATA_P
NC
(MLB)
UNU
S
ED (MLB port)
—
—
B10 MLB_DATA_N
NC
(MLB)
UNU
S
ED (MLB port)
—
—
F15
gpmi.NAND_CE0_B NANDF_C
S
0 NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
C16 gpio6.GPIO6_IO14
NC
UNU
S
ED O(L)
Input
PU
(47K)
A17 gpio6.GPIO6_IO15
NC
UNU
S
ED O(L)
Input
PU
(100K)
D16 gpio6.GPIO6_IO16
NC
UNU
S
ED O(L)
Input
PU
(100K)
A16
gpmi.NAND_ALE NANDF_ALE
NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
C15
gpmi.NAND_CLE NANDF_CLE
NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
E15
gpmi.NAND_WP_B NANDF_WP_B NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
B16
gpmi.NAND_READY NANDF_RB0 NAND
FLA
S
H CONTROL
O
Input
PU
(100K)
PU
3
k
A1
8
gpmi.NAND_DATA00 NANDF_D0 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
C17
gpmi.NAND_DATA01 NANDF_D1 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
F16
gpmi.NAND_DATA02 NANDF_D2 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
D17
gpmi.NAND_DATA0
3
NANDF_D
3
NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
A19
gpmi.NAND_DATA04 NANDF_D4 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
B1
8
gpmi.NAND_DATA05 NANDF_D5 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
E17
gpmi.NAND_DATA06 NANDF_D6 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
C1
8
gpmi.NAND_DATA07 NANDF_D7 NAND
FLA
S
H CONTROL
IO
Input
PU
(100K)
B1 PCIE_RX_N
NC
(PCIE)
UNU
S
ED
(PCIE
port)
—
—
B2 PCIE_RX_P
NC
(PCIE)
UNU
S
ED
(PCIE
port)
—
—
A
3
PCIE_TX_N
NC
(PCIE)
UNU
S
ED
(PCIE
port)
—
—
B
3
PCIE_TX_P
NC
(PCIE)
UNU
S
ED
(PCIE
port)
—
—
D21
gpio6.GPIO6_IO19
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PD
(100K)
C22 gpio6.GPIO6_IO20
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
F20 gpio6.GPIO6_IO21
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
E21
gpio6.GPIO6_IO22
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
A24 gpio6.GPIO6_IO2
3
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
C2
3
gpio6.GPIO6_IO26
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PD
(100K)
B25 gpio6.GPIO6_IO
3
0
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PD
(100K)
C24 gpio6.GPIO6_IO25
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
B2
3
gpio6.GPIO6_IO27
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
B24 gpio6.GPIO6_IO2
8
NC (RGMII) *1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
D2
3
gpio6.GPIO6_IO29
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PU
(100K)
D22 gpio6.GPIO6_IO24
NC
(RGMII)
*1.5V
UNU
S
ED (RGMII port)
VOLTAGE CAUTION (GPIO 1.5V)
Input
PD
(100K)
K1 HDMI_TX_HPD
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
J5 HDMI_TX_CLK_N
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
J6 HDMI_TX_CLK_P
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
K5 HDMI_TX_DATA0_N
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
K6 HDMI_TX_DATA0_P
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
J
3
HDMI_TX_DATA1_N
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
J4 HDMI_TX_DATA1_P
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
K
3
HDMI_TX_DATA2_N
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
K4 HDMI_TX_DATA2_P
NC
(HDMI)
UNU
S
ED
(HDMI
port)
—
—
U2 LVD
S
0_DATA0_N LVD
S
0_TX0_N LCD
CONTROL(LVD
S
)
O
—
—
U1 LVD
S
0_DATA0_P LVD
S
0_TX0_P LCD
CONTROL(LVD
S
)
O
Input
Keeper
U4 LVD
S
0_DATA1_N LVD
S
0_TX1_N LCD
CONTROL(LVD
S
)
O
—
—