Phytec phyCORE-i.MX31, Hardware Manual

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System Memory
©
PHYTEC Messtechnik GmbH 2007 L-700e_0
31
7.1 Memory Model
The i.MX31 memory map is summarized in Table 5 below. For a detailed view of the memory map
please consult the
Freescale i.MX31 User’s Manual .
Table 5: i.MX31 memory map
A
DDRESS
C
HIP
-S
ELECT
F
UNCTION
0x8000 00000 – 0x8FFF FFFF
/CSD0 (/CS2) LP-DDR-SDRAM Bank 0 (U5,
U7)
0x9000 00000 – 0x9FFF FFFF
/CSD1 (/CS3) LP-DDR-SDRAM Bank 1 (U6,
U8)
0xA000 00000 – 0xA7FF FFFF /CS0 NOR-Flash (U15)
0xA800 00000 – 0xAFFF
FFFF /CS1
Ethernet Controller (U3)
0xB400 00000 – 0xB5FF FFFF /CS4 SRAM (U19)
0xB600 00000 – 0xB6FF FFFF
/CS5 not used on phyCORE-i.MX31
(SJA1000 on Carrier Board)