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System Memory 

 

 

 

 

 

©

 PHYTEC Messtechnik GmbH 2007     L-700e_0 

13

 

27B 

x_/EB0 

O 

3.3V 

X_/EB0 corresponds to DATA_OUT[7:0] and 
M_DATA_OUT[7:0]. 

28B x_/WR 

O 

3.3V 

/Write 

Signal. 

29B GND 

-

 

0

 

Ground 0V 

30B 

x_WAIT 

I 

3.3V 

End current burst (/WAIT 

31B x_A0 

O 

3.3V 

Address-Line 

A0 

32B x_A1 

O 

3.3V 

Address-Line 

A1 

33B x_A3 

O 

3.3V 

Address-Line 

A3 

34B GND 

- 

0 

Ground 

0V 

35B x_A6 

O 

3.3V 

Address-Line 

A6 

36B x_A8 

O 

3.3V 

Address-Line 

A8 

37B x_A9 

O 

3.3V 

Address-Line 

A9 

38B x_A11 

O 

3.3V 

Address-Line 

A11 

39B GND 

- 

0 

Ground 

0V 

40B x_A14 

O 

3.3V 

Address-Line 

A14 

41B x_A16 

O 

3.3V 

Address-Line 

A16 

42B x_A17 

O 

3.3V 

Address-Line 

A17 

43B x_A19 

O 

3.3V 

Address-Line 

A19 

44B GND 

- 

0 

Ground 

0V 

45B x_A22 

O 

3.3V 

Address-Line 

A22 

46B x_A24 

O 

3.3V 

Address-Line 

A24 

47B x_A25 

O 

3.3V 

Address-Line 

A25 

48B x_D1 

I/O 

3.3V 

Data-Bus 

D1 

49B GND 

- 

0 

Ground 

0V 

50B x_D4 

I/O 

3.3V 

Data-Bus 

D4 

51B x_D6 

I/O 

3.3V 

Data-Bus 

D6 

52B x_D7 

I/O 

3.3V 

Data-Bus 

D7 

53B x_D9 

I/O 

3.3V 

Data-Bus 

D9 

54B GND 

- 

0 

Ground 

0V 

55B x_D12 

I/O 

3.3V 

Data-Bus 

D12 

56B x_D14 

I/O 

3.3V 

Data-Bus 

D14 

57B x_D15 

I/O 

3.3V 

Data-Bus 

D15 

58B 

x_/FL_WP 

I 

3.3V 

Flash Protection Signal 

59B GND 

-

 

0

 

Ground 0V 

60B 

x_/PC_CD2 

I 

NVCC_3_4_6 PCMCIA Card Detect Input 2 

61B 

x_PCPOE 

O 

NVCC_3_4_6 PCMCIA buffers output enable 

62B x_PC_READY 

I  NVCC_3_4_6 PCMCIA 

Ready 

63B 

x_PC_RST 

O 

NVCC_3_4_6 PCMCIA Card Reset. 

64B GND 

-

 

0

 

Ground 0V 

65B x_/PC_WAIT 

I  NVCC_3_4_6 PCMCIA Extend bus cycle. Input 

66B 

x_/CE2 

O 

NVCC_3_4_6 PCMCIA Card Enable 2 Signal 

Summary of Contents for phyCORE-i.MX31

Page 1: ...phyCORE i MX31 HARDWARE MANUAL EDITION JULY 2007 A product of a PHYTEC Technology Holding company...

Page 2: ...sstechnik GmbH offers no guarantee nor accepts any liability for damages arising from the improper usage or improper installation of the hardware or software PHYTEC Messtechnik GmbH further reserves t...

Page 3: ...32 Transceiver U21 39 7 6 1 UART3 Routing RN47 40 8 USB OTG Transceiver U22 41 9 Ethernet Controller U3 42 10 JTAG Interface X2 43 11 Technical Specifications 48 12 Hints for Handling the phyCORE i MX...

Page 4: ...CD Pin Header X23 89 13 5 15 Serial LCD X24 93 13 5 16 Camera Interface X7 X8 95 13 5 17 JTAG Interface X6 100 13 5 18 Expansion Bus Connectors 102 13 5 19 Carrier Board Physical Dimensions 115 13 6 S...

Page 5: ...rier Board Connection Using the phyMAPPER i MX31 52 Figure 12 Modular Development and Expansion Board Concept with phyCORE i MX31 53 Figure 13 Carrier Board Connector Locations 55 Figure 14 Typical Ju...

Page 6: ...phyCOREi MX31 PHYTEC Messtechnik GmbH 2007 L 700e_0 Figure 26 phyCORE i MX31 Component Placement Top View 120 Figure 27 phyCORE i MX31 Component Placement Bottom View121...

Page 7: ...Write Protection States 38 Table 11 RN47 UART3 Routing 40 Table 12 Ethernet Controller Memory Map 42 Table 13 JTAG Connector X2 Signal Assignment 46 Table 14 Carrier Board Connectors 54 Table 15 Carri...

Page 8: ...31 Zigbee Connector 85 Table 29 Universal Display Pin Header 90 Table 30 Display switch Universal pin header 92 Table 34 Serial LCD pin header 93 Table 35 PHYTEC Camera Connector X7 97 Table 36 Unive...

Page 9: ...Contents PHYTEC Messtechnik GmbH 2007 L 700e_0...

Page 10: ......

Page 11: ...e operated without protection circuitry if connections to the product s pin header rows are longer than 3 m PHYTEC products fulfill the norms of the European Union s Directive for Electro Magnetic Con...

Page 12: ...ng EMI and EMC guidelines using phyCORE boards even in high noise environments phyCORE boards achieve their small size through modern SMD technology and multi layer design In accordance with the compl...

Page 13: ...one UART at data rates of up to 460kbps Two full featured UART Interfaces without transceiver 32KB I2 C EEPROM Separate I C RTC with backup function 512Kbyte up to 2MByte SRAM with backup function Ba...

Page 14: ...phyCOREi MX31 1 2 Block Diagram Figure 1 Block Diagram of the phyCORE i MX31 4 PHYTEC Messtechnik GmbH 2007 L 700e_0...

Page 15: ...30 C159 C135 C134 R2 R80 R32 C165 R93 C151 U11 C163 RN21 TP1 C153 R57 R79 C1 D2 J18 D7 C101 R38 RN6 CB301 C10 CB401 R56 XT1 R37 RN43 CB502 RN35 C3 R90 R88 R49 RN14 R74 CB501 R58 RN36 RN25 CB100 C156 R...

Page 16: ...1 R34 C4 C86 C114 RN1 R35 C50 C148 RN34 C150 C138 C45 C27 R36 J1 CB305 J21 Q4 C61 CB251 RN45 R51 R47 R19 Q1 C93 U16 RN46 C59 RN2 C52 C139 C14 RN31 C137 C87 C67 XT2 CB302 RN44 RN33 RN8 C6 R52 C70 R53 R...

Page 17: ...e pin connector rows progresses alphabetically from left to right refer to Figure 4 The numbered matrix can be aligned with the phyCORE i MX31 viewed from above phyCORE connector pointing down or with...

Page 18: ...vel interface voltages listed in the SL Signal Level column The Freescale i MX31 is a multi voltage operated microcontroller and as such special attention should be paid to the interface voltage level...

Page 19: ...x_LC_ D3_SPL O NVCC_7 SPL signal for Sharp display 3 10A x_LC_ DRDY0 O NVCC_7 Keyboard row 4 scan output pin of the C 11A x_LC_FPLINE O NVCC_7 Display 3 horizontal synchronization pulse FPLINE HSYNC L...

Page 20: ...Address Line A21 46A x_A23 O 3 3V Address Line A23 47A GND 0 Ground 0V 48A x_D0 I O 3 3V Data Bus D0 49A x_D2 I O 3 3V Data Bus D2 50A x_D3 I O 3 3V Data Bus D3 51A x_D5 I O 3 3V Data Bus D4 52A GND 0...

Page 21: ..._3_4_6 ATA data bus D3 81A x_ATA_DATA5 I O NVCC_3_4_6 ATA data bus D5 82A GND 0 Ground 0V 83A x_ATA_DATA8 I O NVCC_3_4_6 ATA data bus D8 84A x_ATA_DATA10 I O NVCC_3_4_6 ATA data bus D10 85A x_ATA_DATA...

Page 22: ...T DOTCLC LSCLC DCLK CLOCK inputs of supported displays 11B x_LC_x_LCS0 O NVCC_7 Chip select signal for the for the asynchronous smart primary display display 0 12B x_LC_x_LCS1 O NVCC_7 Chip select sig...

Page 23: ...ess Line A19 44B GND 0 Ground 0V 45B x_A22 O 3 3V Address Line A22 46B x_A24 O 3 3V Address Line A24 47B x_A25 O 3 3V Address Line A25 48B x_D1 I O 3 3V Data Bus D1 49B GND 0 Ground 0V 50B x_D4 I O 3...

Page 24: ...ATA_DATA4 I O NVCC_3_4_6 ATA data bus D4 81B x_ATA_DATA6 I O NVCC_3_4_6 ATA data bus D6 82B x_ATA_DATA7 I O NVCC_3_4_6 ATA data bus D7 83B x_ATA_DATA9 I O NVCC_3_4_6 ATA data bus D9 84B GND 0 Ground 0...

Page 25: ...tery current sensing point 1 15C x_BATTFET O VATLAS Driver output for battery path FET 16C x_CHRGISNSP I VATLAS Charge current sensing point 1 17C GND 0 Ground 0V 18C x_LICELL I MV 1 Coincell supply i...

Page 26: ...Analog Input Channel 7 47C GND 0 Ground 0V 48C x_ADOUT O LV VIOLO ADC trigger output 49C X_ADTRIG I LV VIOLO ADC trigger input 50C x_ LOWBAT O LV VIOLO Low battery indicator signal or end of life ind...

Page 27: ...CTS_DTE2_TTL O NVCC_8 Clear to send UART2 80C x_DSR_DTE2_TTL I NVCC_8 Data set ready UART2 81C x_DCD_DTE2_TTL I NVCC_8 Data carrier detected UART2 82C GND 0 Ground 0V 83C x_I2C2_SCL I O NVCC_5_10 I C...

Page 28: ...ger Input 13D x_Charger_Input I EHV Charger Input 14D GND 0 Ground 0V 15D x_CHRGISNSN I VATLAS Charge current sensing point 2 16D x_BFET O EHV 1 Driver output for dual path regulated BP FET 2 Driver o...

Page 29: ...VCC_3_4_6 JTAG Mode 44D GND 0 Ground 0V 45D x_ADIN8 O LV VIOLO Analog Input Channel 8 46D x_ADIN9 O LV VIOLO Analog Input Channel 9 47D x_ADIN10 O LV VIOLO Analog Input Channel 10 48D x_ADIN11 O LV VI...

Page 30: ..._DTE2_TTL I NVCC_8 Request to send UART2 79D GND 0 Ground 0V 80D x_RI_DTE2_TTL I NVCC_8 Ring indicator UART2 81D x_DTR_DTE2_TTL O NVCC_8 Data terminal ready UART2 82D x_MCU2_16 I O NVCC_3_4_6 GPIO MCU...

Page 31: ...ed on the top side of the module opposite side of connectors and 16 solder jumpers are located on the bottom side of the module connector side Table 2 below provides a functional summary of the solder...

Page 32: ...phyCOREi MX31 J20 J18 J19 J16 J17 Figure 6 Jumper locations top view 22 PHYTEC Messtechnik GmbH 2007 L 700e_0...

Page 33: ...System Memory J2 J3 J8 JN2 J6 JN1 J4 J1 J21 J5 J13 J10 J11 J14 J15 J12 J9 J22 J7 Figure 7 Jumper locations bottom view PHYTEC Messtechnik GmbH 2007 L 700e_0 23...

Page 34: ...is not write protected closed EEPROM U17 is write protected 7 5 J7 open RAM Bank input is high only DDR RAM bank 0 is populated closed RAM Bank input is low DDR RAM bank s 0 1 are populated J9 open W...

Page 35: ...nnected to VATLAS high open CHRGMOD1 is floating high z N A J19 1 2 RXOUTL is connected to X1 pin 23C 2 3 LSPP is connected to X1 pin 23C J20 2 3 RXOUTR is connected to X1 pin 24C 2 3 LSPM is connecte...

Page 36: ...CC_3V3 together and supply both inputs with a 3 3V input voltage This will both simplify the design and reduce the component count The input voltage range of VIN is from 3 1V 4 65V with a nominal curr...

Page 37: ...700e_0 27 VESIM NVCC_9 2 775V VCAM NVCC_7 2 775V VRF1 NVCC_5_10 2 775V In general you should not need to adjust the Power up Mode settings The configuration has been optimized for the phyCORE i MX31...

Page 38: ...means of time memory keeping in the absence of power at the VCC_3V3 pins while drawing minimal power from the battery The x_VBAT 2 0V x_VBAT VCC_3V3 input operating limits are listed in Table 4 below...

Page 39: ...iguration Although most features of the Freescale phyCORE i MX31 microcontroller are configured and or pro grammed during the initialization routine other features which impact program execution must...

Page 40: ...DDR SDRAM 128MByte up to 256MByte SRAM 512KByte up to 2MByte NAND Flash 64MByte up to 1GByte NOR Flash 32MByte up to 64MByte I C EEPROM 32KB up to 32KByte It should be noted that the LP DDR SDRAM has...

Page 41: ...er s Manual Table 5 i MX31 memory map ADDRESS CHIP SELECT FUNCTION 0x8000 00000 0x8FFF FFFF CSD0 CS2 LP DDR SDRAM Bank 0 U5 U7 0x9000 00000 0x9FFF FFFF CSD1 CS3 LP DDR SDRAM Bank 1 U6 U8 0xA000 00000...

Page 42: ...density configurations U6 and U8 are also populated and are accessed via SDRAM memory bank 1 using chip select signal CSD1 starting at 0x9000 0000 If RAM bank U6 U8 is unpopulated then the CSD1 chip s...

Page 43: ...0 which is located at memory address 0xA000 0000 The entire Flash can be write protected by pulling the x_ FL_WP signal located at the phyCORE connector X1 on pin 58B low The following NOR Flash devic...

Page 44: ...FACTURER NAND FLASH P N DENSITY MBYTE ST Microelectronics NAND512W3A2CN6 64 Additionally any parts that are footprint TSOP48 and functionally compatible with the NAND Flash devices listed above may al...

Page 45: ...Bit and 16 Bit NAND Flash devices To select between 8 and 16 Bit NAND Flash the jumpers resistor networks must be populated as follows Table 8 JN1 2 RN41 42 NAND Flash bit width selection1 NAND FLASH...

Page 46: ...ORE connector as x_I2C2_SDA on X1 pin 84C and x_I2C2_SCL on X1 pin 83C Three solder jumpers are provided to set the lower address bits J4 J5 and J6 Refer to section 7 5 1 for details on setting these...

Page 47: ...address bits of the seven bit I C device address are configurable using jumpers J4 J5 and J6 J4 sets address bit A0 J5 address bit A1 and J6 address bit A2 Table 9 below shows the resulting seven bit...

Page 48: ...the EEPROM U17 device Closing this jumper allows write access to the device while opening this jumper enables write protection The following configurations are possible Table 10 EEPROM write protectio...

Page 49: ...while the TxD line of the transceiver is connected to the RxD line of the COM port The ground potential of the phyCORE i MX31 circuitry needs to be connected to the applicable ground pin on the COM p...

Page 50: ...to these same pins The standard phyCORE i MX31 module will have U21 populated thereby routing the RS 232 level signals to the phyCORE connector Be sure the phyCORE i MX31 configuration you are workin...

Page 51: ...ow speed data rates The ISP1504 functions as the transceiver between the i MX31 Host Controller Device Controller and On The Go Controller An external USB Standard A for USB host USB Standard B for US...

Page 52: ...he Ethernet controller is connected to the address data bus with a 16 bit width and x_GPIO3_1 as interrupt The interrupt is being used as active low edge triggered The CS signal is connected to the i...

Page 53: ...internal controller RAM or for debugging programs currently executing The JTAG interface extends out to a 2 0 mm pitch pin header at X2 on the edge of the module PCB Figure 8 and Figure 9 show the pos...

Page 54: ...ORE i MX31 modules with order code PCM 037 D JTAG connector X2 is not populated on phyCORE modules with order code PCM 037 However all JTAG signals are also accessible at the phyCORE connector X1 Mole...

Page 55: ...Debug Interface X201 PHYTEC Messtechnik GmbH 2007 L 700e_0 45...

Page 56: ...x_CPU_ DE GND 20 19 J_DBGACK 10k Ohm pulldown Note Row A is on the controller side of the module and row B is connector side of the module PHYTEC offers a JTAG Emulator adapter order code JA 002 for...

Page 57: ...Debug Interface X201 PHYTEC Messtechnik GmbH 2007 L 700e_0 47...

Page 58: ...nent height of 4 0 mm on the bottom connector side of the PCB and approximately 3 0 mm on the top microcontroller side The board itself is approximately 1 4 mm thick Values in Bold Italic are TBD 3 6m...

Page 59: ...perating temperature 0 C to 70 C commercial 40 C to 85 C industrial Humidity 95 r F not condensed Operating voltage VIN 3 1V to 4 6V VBAT TBD to TBDV Power consumption VCC 3 3 V 000mA typical Conditio...

Page 60: ...e Should this nonetheless be necessary please ensure that the board as well as surrounding components and sockets remain undamaged while de soldering Overheating the board can cause the solder pads to...

Page 61: ...ith all mechanical and electrical components necessary for the speedy and secure start up and subsequent communication to and programming of applicable PHYTEC Single Board Computer SBC modules Carrier...

Page 62: ...ers all essential components and connectors for start up and connection to processor peripherals The phyMAP i MX31 maps the signals from the phyCORE i MX31 module to the i MX Carrier Board The phyMAP...

Page 63: ...rrier Board Expansion Bus Connectors Patch Field Figure 12 Modular development and expansion board concept with phyCORE i MX31 The following sections contain specific information relevant to the opera...

Page 64: ...ker output connector X13 Stereo Line In input connector X15 Security Digital MultiMedia Card socket X16 USB On The Go connector X17 USB Host connector X18 Keypad pin header connector 2 8 pins 2 mm spa...

Page 65: ...according to use and application it is the user s responsibility to take appropriate safety measures to ensure that the module connections are protected from overloading through connected peripherals...

Page 66: ...ble section in this manual for setting the associated jumpers See Table 15 for default settings and descriptions of all Carrier Board jumpers Figure 14 Typical jumper numbering scheme Figure 14 illust...

Page 67: ...mper descriptions1 JUMPER SETTING DESCRIPTION SEE SECTION JP1 Open Closed RS 232 transceivers are enabled RS 232 transceivers are disabled JP2 Open Closed RS 232 auto shutdown is disabled RS 232 auto...

Page 68: ...in a single daisy chain 13 5 17 JP13 Open Closed USB Host transceiver is disabled USB Host transceiver is enabled 13 5 12 JP14 Open Closed VCC_FUSE 2 775V no FUSE programming VCC_FUSE 3 3V use only fo...

Page 69: ...3 5 4 6 Power source is Power Over Ethernet Power source is 5V adapter 13 5 9 1 JP32 1 3 2 4 3 5 4 6 No power switching direct supply from VCC_3V3 Separate supply path JP33 1 2 3 4 Open Ope n No power...

Page 70: ...spite the signal differences the phyMAP i MX31 board serves as the gateway to properly map signals from the i MX Carrier Board Molex connectors to the various phyCORE i MX module connectors via jumper...

Page 71: ...S4 x_ CS5 x_ CS3 J2 1 2 4 2 3 2 x_CAN_INT x_MCU3_2 x_MC2_16 x_MCU2_1 J3 1 2 4 2 3 2 x_TRIGGER x_MCU3_2 x_ ATA_RESET x_MCU2_1 J4 1 2 4 2 3 2 x_SNAPSHOT x_MCU3_3 x_ ATA_DMACK x_MCU2_2 J5 1 2 4 2 3 2 x_C...

Page 72: ...oard This section describes the functional components of the phyCORE i MX Carrier Board supporting the phyCORE i MX31 Each subsection details a particular connector interface and associated jumpers fo...

Page 73: ...use a laboratory adapter to supply power to the Carrier Board Power spikes during power on could destroy the phyCORE module mounted on the Carrier Board Do not change modules or jumper settings while...

Page 74: ...gle Path Charging It is possible to connect the battery which can power or to be charged by the baseboard on the connector X21 On the connector X20 a Coincell can be connected to use this one as backu...

Page 75: ...3 5 2 Fuse Jumper JP14 Attention see manual This jumper allow modification of internal fuse state Table 17 FUSE jumper1 JUMPER SETTING DESCRIPTION JP14 Open Closed VCC_FUSE 2 775V no FUSE programming...

Page 76: ...nector P1 provides a connection interface to the i MX UART1 and UART3 serial interfaces P1 is a dual stack DB9 connector divided into two sub connectors called P1A bottom connector and P1B top connect...

Page 77: ...en position enabling the RS 232 transceivers Alternatively this jumper can be set to the closed position disabling the RS 232 transceivers Disabling the UART1 RS 232 transceivers can be useful for con...

Page 78: ...1 JUMPER SETTING DESCRIPTION JP1 Open Closed UART1 RS 232 transceivers are enabled UART1 RS 232 transceivers are disabled JP2 Open Closed UART1 RS 232 transceivers have auto shutdown enabled UART1 RS...

Page 79: ...should be noted that the standard phyCORE i MX31 module provides the UART3 signals x_CTS_RS232 x_RTS_RS232 x_RXD_RS232 and x_TDX_RS232 at RS 232 levels Configuration jumpers on the module allow for TT...

Page 80: ...r P2 is connected to the CAN interface of the phyCORE i MX31 via jumpers Controller Area Network CAN is a broadcast differential serial bus standard for connecting electronic control units and was spe...

Page 81: ...nfigurations are possible 1 CAN is supplied via on board power supply Table 19 CAN on board supply JUMPER SETTING DESCRIPTION JP9 1 2 CANV is connected to VCC_5V JP11 1 2 CANV is connected to GND 2 CA...

Page 82: ...buttons and LEDs for input feedback and status purposes A detailed description of each button and LED is presented below S1 Issues a system reset signal Momentarily pressing this button will toggle th...

Page 83: ...rol buttons REFERENCE DESGINATOR SIGNAL DESCRIPTION S1 x_ Reset_Btn RESET S2 x_ ON1 POWER ON S3 x_ ON2 SUSPEND S4 x_ ON3 STANDBY The i MX Carrier Board LEDs provide a variety of status conditions alon...

Page 84: ...arrier Board LEDs REFERENCE DESGINATOR COLOR DESCRIPTION D21 green State of VCC_5V D22 green State of VCC_3V3 D23 green State of VIN D42 red x_Charger_Input D41 red x_CHRGLED D40 red programmable LED...

Page 85: ...CKIH 26MHz is used as clock source Table 24 Boot_Mode2 selection STATE OF SW NUMBER 3 STATE OF SW NUMBER 4 STATE OF X_BOOT_MODE0 BOOT_MODE2 ON OFF 0 OFF ON 1 Table 25 Boot_Mode4 selection STATE OF SW...

Page 86: ...phyCOREi MX31 On NOR Flash On NAND Flash 76 PHYTEC Messtechnik GmbH 2007 L 700e_0...

Page 87: ...ard 13 5 6 Keypad X18 Figure 24 Keypad interface at connector X2 The 2 00mm pin header connector X18 provides access to the i MX31 keypad port signals The pin out of X18 is shown in Table 27 below PHY...

Page 88: ...e 27 Keypad connector X18 signal map PIN NUMBER SIGNAL 1A VCC_3V3 1B VCC_3V3 2A x_KEY_COL0 2B x_KEY_COL1 3A x_KEY_COL2 3B x_KEY_COL3 4A x_KEY_COL4 4B x_KEY_COL5 5A x_KEY_ROW0 5B x_KEY_ROW1 6A x_KEY_RO...

Page 89: ...h CF interface is available on the baseboard at X10 Compact Flash can be data storage cards but now a variety of devices like Wi Fi Ethernet adapters The signal x_EXP007 manage the CF power and can be...

Page 90: ...phyCOREi MX31 80 PHYTEC Messtechnik GmbH 2007 L 700e_0 JP17 more info JP604 more info...

Page 91: ...he Development Board 13 5 8 Security Digital Card MultiMedia Card X15 Figure 26 SD Card interface at connector X15 A Security Digital interface is available on the baseboard at X15 PHYTEC Messtechnik...

Page 92: ...ce is supplemented on the baseboard by the Ethernet transformer and the RJ45 connector The Ethernet interface is accessible on the RJ45 socket at X27 The yellow LED extends to the x_ETH_ LED1 signal S...

Page 93: ...r the baseboard with Power Over Ethernet JP31 must be closed on pins 1 3 and 2 4 This technology enables to transmit power along with data over standard network cables The theoretical current limit is...

Page 94: ...n for a suite of high level communication protocols using small low power digital radios based on the IEEE 802 15 4 standard For this feature the Freescale MC13192 RF daughter card1 should be plugged...

Page 95: ...table below Table 28 Zigbee connector PIN NUMBER SIGNAL NAME 1 to 18 Not connected 19 x_ IRQ 20 x_ Reset_Btn 21 to 34 Not connected 35 x_MOSI 36 x_SPICLK 37 x_CE 38 x_MISO 39 VCC_ZIGBEE 40 GND For mo...

Page 96: ...tem was designed by Dallas Semiconductor and provides low speed data signaling and power over a single wire a ground wire is also needed One Wire is similar in concept to I C but with lower data rates...

Page 97: ...t Board 13 5 12 USB Host X17 Figure 31 USB host interface at connector X17 The controller supports control of input USB devices such keyboard mouse or USB key The connector type of X17 is USB A PHYTEC...

Page 98: ...e controller supports the On The Go feature The Universal Serial Bus On The Go is a device capable to initiate the session control the connection and exchange Host Peripheral roles between each other...

Page 99: ...PHYTEC provides a compatible Sharp 240x320 TFT LCD that connects directly to X23 X23 can also be used to connect a compatible LCD to the i MX31 for customer specific applications Table 29 provides a d...

Page 100: ...lue data 2 11 LCD_B3 Blue data 3 12 LCD_B4 Blue data 4 13 LCD_B5 Blue data 5 14 GND Ground 15 LCD_G0 Green data 0 16 LCD_G1 Green data 1 17 LCD_G2 Green data 2 18 LCD_G3 Green data 3 19 LCD_G4 Green d...

Page 101: ...ON position otherwise the output will be floating SW1 2 Controls the vertical orientation of the picture Flipping this switch will cause the picture to mirror vertically In the ON position the output...

Page 102: ...may be useful when connecting your own LCD to the i MX Carrier Board Table 30 below provides a summary of the SW1 dipswitch functions Table 30 SW1 LCD switch operation SWITCH NUMBER DESCRIPTION 1 Left...

Page 103: ...re 34 Serial LCD interface at connector X24 Furthermore there is a 2 mm connector to connect a serial LCD The pinout of this connector X24 is shown in the table below Table 31 Serial LCD pin header PI...

Page 104: ...VCC_3V3 Power 1B VCC_3V3 Power 2A SLCD_CLK Serial LCD clock 2B SLCD_D0 Serial LCD data 3A SLCD_RS Serial LCD reset 3B SLCD_CS Serial LCD chip select 4A GND Power 4B GND Power These LCD signals are dec...

Page 105: ...Development Board 13 5 16 Camera Interface X7 X8 Figure 35 Camera interface at connectors X7 and X8 The CSI signals are decoupled from the module with 74LVC254 line driver circuits PHYTEC Messtechnik...

Page 106: ...ules which can be directly connected to X7 on the baseboard ORDERING NUMBER MAIN FEATURES VM 006 BW xxx 1 2 SXGA 1280 H x 1024 V MICRON MT9M001 VM 007 BW xxx 1 3 Wide VGA 752 H x 480 V MICRON MT9V022S...

Page 107: ..._PCLK Pixel clock input 8 GND Ground 9 CAM1_DD0 Data 0 10 CAM1_DD1 Data 1 11 GND Ground 12 CAM1_DD2 Data 2 13 CAM1_DD3 Data 3 14 GND Ground 15 CAM1_DD4 Data 4 16 CAM1_DD5 Data 5 17 GND Ground 18 CAM1_...

Page 108: ...IGNAL NAME DESCRIPTION 1A VCC_CAM_EXT External power supply 1B VCC_CAM_EXT External power supply 2A VCC_3V3 Power supply 2B VCC_3V3 Power supply 3A x_RESET_3V3 Reset 3B CAM1_SDA SDA Quick Capture 4A C...

Page 109: ...The phyCORE i MX on the Development Board PHYTEC Messtechnik GmbH 2007 L 700e_0 99 15A x_TRIGGER Trigger 15B GND Ground...

Page 110: ...es a JTAG interface for debuggers and emulators All JTAG interface signals extend from the phyCORE connector to an ARM compatible dual row 20 pin connector at X6 Table 34 below describes the pin assig...

Page 111: ...PHYTEC Messtechnik GmbH 2007 L 700e_0 101 1 VCC_JTAG 2 VCC_JTAG 3 x_CPU_ TRST 4 GND 5 x_CPU_TDI 6 GND 7 x_CPU_TMS 8 GND 9 x_CPU_TCK 10 GND 11 x_CPU_RTCK 12 GND 13 x_CPU_TDO 14 GND 15 x_CPU_SRST 16 GN...

Page 112: ...iew of the pin labeling on the expansion bus To connect to X2 PHYTEC provides a bare expansion interface PCB for prototyping purposes The bare PCB contains a grid of solder holes along with a patch fi...

Page 113: ...x_LC_D3_REV x_LC_D3_REV X14 2 9A x_LC_D3_SPL x_LC_D3_SPL X15 2 10A x_LC_DRDY0 x_LC_DRDY0 X16 2 11A x_LC_FPLINE x_LC_FPLINE X17 2 12A GND GND GND 13A x_LC_D0 x_LC_D0 X14 4 14A x_LC_D2 x_LC_D2 X15 4 15A...

Page 114: ...A x_D9 x_D9 X15 12 50A x_D10 x_D10 X16 12 51A x_D12 x_D12 X17 12 52A GND GND GND 53A x_ OE x_ OE X14 14 54A x_LBA x_LBA X15 14 55A x_ WR x_ WR X16 14 56A VCC_CAN NVCC_8 X17 14 57A GND GND GND 58A x_ C...

Page 115: ...82A GND GND GND 83A x_USBHOST2_CLK x_USBHOST2_CLK X14 21 84A x_USBHOST2_DIR x_USBHOST2_DIR X15 21 85A x_USBHOST2_DA0 x_USBHOST2_DA0 X16 21 86A x_USBHOST2_DA2 x_USBHOST2_DA2 X17 21 87A GND GND GND 88A...

Page 116: ...x_LC_D3_CLS X13 2 9B GND GND GND 10B x_LC_BCLK x_LC_BCLK X10 4 11B x_LC_x_LCS0 x_LC_x_LCS0 X11 4 12B x_LC_x_LSC1 x_LC_x_LSC1 X12 4 13B x_LC_D1 x_LC_D1 X13 4 14B GND GND GND 15B x_LC_D4 x_LC_D4 X10 5 1...

Page 117: ..._D11 x_D11 X10 14 51B x_D13 x_D13 X11 14 52B x_D14 x_D14 X12 14 53B x_D15 x_D15 X13 14 54B GND GND GND 55B x_ EB0 x_ EB0 X10 15 56B x_ EB1 x_ EB1 X11 15 57B x_ CE1 x_ CE1 X12 15 58B x_ CE2 x_ CE2 X13...

Page 118: ...1 83B x_USBHOST2_NXT x_USBHOST2_NXT X13 21 84B GND GND GND 85B x_USBHOST2_DA1 x_USBHOST2_DA1 X10 22 86B x_USBHOST2_DA3 x_USBHOST2_DA3 X11 22 87B x_USBHOST2_DA4 x_USBHOST2_DA4 X12 22 88B x_USBHOST2_DA6...

Page 119: ...0C VCC_3V3 VCC_3V3 X9 1 11C VCC_3V3 VCC_3V3 X9 2 12C GND GND GND 13C x_TSX1 x_TSX1 X5 4 14C x_TSX2 x_TSX2 X7 4 15C x_TSY1 x_TSY1 X8 4 16C x_TSY2 x_TSY2 X2 5 17C GND GND GND 18C x_VBAT x_VBAT X5 5 19C...

Page 120: ...W X5 12 49C x_EXP017 x_ATA_DA0 X7 12 50C x_EXP018 x_ATA_DA1 X8 12 51C x_EXP020 x_ATA_DATA14 X2 14 52C GND GND GND 53C x_EXP023 x_ ATA_DMACK X5 14 54C x_EXP025 x_GPIO1_1 X7 14 55C x_EXP026 x_GPIO1_2 X8...

Page 121: ...Y X7 20 80C x_EXP066 x_MCU2_0 X8 20 81C x_EXP068 x_MCU2_2 X2 21 82C GND GND GND 83C x_EXP071 x_MCU3_2 X5 21 84C x_EXP073 x_MCU1_25 X7 21 85C x_EXP074 x_MCU1_26 X8 21 86C x_EXP076 x_ RESET X2 22 87C GN...

Page 122: ...x_CAN_TXD NC X4 4 13D x_CAN_RXD NC X6 4 14D GND GND GND 15D x_KEY_ROW0 x_KEY_ROW0 X9 4 16D x_KEY_ROW1 x_KEY_ROW1 X3 5 17D x_KEY_ROW2 x_KEY_ROW2 X4 5 18D x_KEY_ROW3 x_KEY_ROW3 X6 5 19D GND GND GND 20D...

Page 123: ...16 x_ATA_DMARQ X6 12 49D GND GND GND 50D x_EXP019 x_ATA_DA2 X9 12 51D x_EXP021 x_ATA_DATA1 X3 14 52D x_EXP022 x_ ATA_RESET X4 14 53D x_EXP024 x_GPIO1_0 X6 14 54D GND GND GND 55D x_EXP027 x_GPIO1_3 X9...

Page 124: ...X9 20 81D x_EXP069 x_MCU2_3 X3 21 82D x_EXP070 x_MCU3_1 X4 21 83D x_EXP072 x_MCU3_3 X6 21 84D GND GND GND 85D x_EXP075 x_Tout X9 21 86D x_EXP077 x_ FL_WP X3 22 87D x_EXP078 x_COMPARE X4 22 88D x_EXP0...

Page 125: ...The phyCORE i MX on the Development Board PHYTEC Messtechnik GmbH 2007 L 700e_0 115 13 5 19 Carrier Board Physical Dimensions TBD...

Page 126: ...CD displays to be connected to the i MX Carrier Board The LCD 004 adapter board connects to the i MX Carrier Board via X1 on the LCD 004 board mating with X23 on the i MX Carrier Board Refer to sectio...

Page 127: ...esstechnik GmbH 2007 L 700e_0 117 In addition to the brightness control the i MX Carrier Board provides dipswitch SW1 to control LCD enable disable and vertical image orientation Refer to section 13 5...

Page 128: ...phyCOREi MX31 118 PHYTEC Messtechnik GmbH 2007 L 700e_0 13 6 1 LCD 004 Physical Dimensions TBD...

Page 129: ...bH 2007 L 700e_0 119 14 Revision History Date Version numbers Changes in this manual 16 July 2007 Manual L 700e_0 PCM 037 PCB 1262 2 PCM 970 PCB 1281 1 First draft Preliminary documentation Describes...

Page 130: ...N30 C159 C135 C134 R2 R80 R32 C165 R93 C151 U11 C163 RN21 TP1 C153 R57 R79 C1 D2 J18 D7 C101 R38 RN6 CB301 C10 CB401 R56 XT1 R37 RN43 CB502 RN35 C3 R90 R88 R49 RN14 R74 CB501 R58 RN36 RN25 CB100 C156...

Page 131: ...C4 C86 C114 RN1 R35 C50 C148 RN34 C150 C138 C45 C27 R36 J1 CB305 J21 Q4 C61 CB251 RN45 R51 R47 R19 Q1 C93 U16 RN46 C59 RN2 C52 C139 C14 RN31 C137 C87 C67 XT2 CB302 RN44 RN33 RN8 C6 R52 C70 R53 R6 C12...

Page 132: ...44 J J603 41 JA 002 49 JTAG Interface 46 JTAG Emulator Adapter 49 N NAND Flash 32 37 O Operating Temperature 52 Operating Voltage 52 P phyCORE connector 8 9 Physical Dimensions 51 Pin Description 8 Pi...

Page 133: ...x PHYTEC Messtechnik GmbH 2007 L 700e_0 123 U600 37 U601 39 U602 35 36 U603 35 36 UART3 42 UART5 42 USB Device 44 USB Host 44 USB On The Go 44 USB OTG 44 USB Transceiver 44 V VBAT 29 W Weight 52 X X20...

Page 134: ...ocument number L 700e_0 Preliminary Version July 2007 How would you improve this manual Did you find any mistakes in this manual page Submitted by Customer number Name Company Address Return to PHYTEC...

Page 135: ...Published by PHYTEC Messtechnik GmbH 2007 Ordering No L 700e_0 Printed in Germany...

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