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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

User manual

Rev. 03 — 7 June 2005

93 of 139

Philips Semiconductors

UM10119

P89LPC938 User manual

In

, SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave.

The SPI master can use any port pin (including P2.4/SS) to drive the SS pin.

shows a case where two devices are connected to each other and either device

can be a master or a slave. When no SPI operation is occurring, both can be configured
as masters (MSTR = 1) with SSIG cleared to 0 and P2.4 (SS) configured in
quasi-bidirectional mode. When a device initiates a transfer, it can configure P2.4 as an
output and drive it low, forcing a mode change in the other device (see

Section 13.4 “Mode

change on SS”

) to slave.

Table 91:

SPI Data register (SPDAT - address E3h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

MSB

LSB

Reset

0

0

0

0

0

0

0

0

Fig 39. SPI single master single slave configuration.

Fig 40. SPI dual device configuration, where either can be a master or a slave.

002aaa901

master

slave

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

8-BIT SHIFT

REGISTER

MISO

MOSI

SPICLK

PORT

MISO

MOSI

SPICLK

SS

002aaa902

master

slave

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

SPI CLOCK

GENERATOR

8-BIT SHIFT

REGISTER

MISO

MOSI

SPICLK

MISO

MOSI

SPICLK

SS

SS

«
...
91
92
93
94
95
...
»

Summary of Contents for P89LPC938

Page 1: ...UM10119 P89LPC938 User manual Rev 03 7 June 2005 User manual Document information Info Content Keywords P89LPC938 Abstract Technical information for the P89LPC938 device ...

Page 2: ...email to sales addresses www semiconductors philips com Revision history Rev Date Description 3 20050607 Corrected typographical error in Table 50 Capture compare control register CCRx address Exh bit description Corrected Table 107 Data EEPROM control register DEECON address F1h bit allocation and Table 108 Data EEPROM control register DEECON address F1h bit description Revised Table 52 Output co...

Page 3: ...standard 80C51 devices Many system level functions have been incorporated into the P89LPC938 in order to reduce component count board space and system cost 1 1 Pin configuration Fig 1 P89LPC938 TSSOP28 pin configuration P89LPC938FDH 002aab101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 P2 0 ICB AD07 P2 1 OCD AD06 P0 0 CMP2 KBI0 AD05 P1 7 OCC AD04 P1 6 OCB P1 5 RST VS...

Page 4: ...CIN2B KBI1 AD00 P0 2 CIN2A KBI2 AD01 P0 3 CIN1B KBI3 AD02 P0 4 CIN1A KBI4 AD03 P0 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 P1 2 T0 SCL P2 2 MOSI P2 3 MISO P2 4 SS P2 5 SPICLK P1 1 RXD P1 0 TXD 002aab073 P89LPC938FHN Transparent top view 7 15 6 16 5 17 4 18 3 19 2 20 1 21 8 9 10 11 12 13 14 28 27 26 25 24 23 22 terminal 1 index area P1 7 OCC AD04 P2 7 ICA P2 1 OCD AD06 P2 0 ICB AD07 P0 0 CMP2 ...

Page 5: ...itt triggered inputs Port 0 also provides various special functions as described below P0 0 CMP2 KBI0 AD05 3 27 I O P0 0 Port 0 bit 0 O CMP2 Comparator 2 output I KBI0 Keyboard input 0 I AD05 ADC0 channel 5 analog input P0 1 CIN2B KBI1 AD00 26 22 I O P0 1 Port 0 bit 1 I CIN2B Comparator 2 positive input B I KBI1 Keyboard input 1 I AD00 ADC0 channel 0 analog input P0 2 CIN2A KBI2 AD01 25 21 I O P0 ...

Page 6: ... 1 bit 2 open drain when used as output I O T0 Timer counter 0 external count input or overflow output open drain when used as output I O SCL I2C serial clock input output P1 3 INT0 SDA 11 7 I O P1 3 Port 1 bit 3 open drain when used as output I INT0 External interrupt 0 input I O SDA I2C serial data input output P1 4 INT1 10 6 I P1 4 Port 1 bit 4 I INT1 External interrupt 1 input P1 5 RST 6 2 I P...

Page 7: ...ort 2 bit 2 I O MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 MISO 14 10 I O P2 3 Port 2 bit 3 I O MISO When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 11 I O P2 4 Port 2 bit 4 I SS SPI Slave select P2 5 SPICLK 16 12 I O P2 5 Port 2 bit 5 I O SPICLK SPI clock When configur...

Page 8: ...lator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 XTAL1 8 4 I O P3 1 Port 3 bit 1 I XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the Flash configuration It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if X...

Page 9: ...OSCILLATOR DIVIDER CPU clock CONFIGURABLE OSCILLATOR ON CHIP RC OSCILLATOR internal bus CRYSTAL OR RESONATOR POWER MONITOR POWER ON RESET BROWNOUT RESET 002aab106 UART ANALOG COMPARATORS 512 BYTE AUXILIARY RAM I2C BUS 512 BYTE DATA EEPROM PORT 3 CONFIGURABLE I Os CCU CAPTURE COMPARE UNIT P89LPC938 WATCHDOG TIMER AND OSCILLATOR TIMER 0 TIMER 1 REAL TIME CLOCK SYSTEM TIMER SPI ADC0 P3 1 0 P2 7 0 P1 ...

Page 10: ...ot attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 ...

Page 11: ...H ADI07 ADI06 ADI05 ADI04 ADI03 ADI02 ADI01 ADI00 00 0000 0000 AD0MOD A ADC0 mode register A C0H BNDI0 BURST0 SCC0 SCAN0 00 0000 0000 AD0MOD B ADC0 mode register B A1H CLK2 CLK1 CLK0 00 000x 0000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 DPS 00 0000 00x0 Bit address F7 F6 F5 F4 F3 F2 F1 F0 B B register F0H 00 0000 0000 BRGR0 2 Baud rate generator rate low BEH 00 0000 0000 B...

Page 12: ...ess low E6H 00 0000 0000 FMCON Program Flash control Read E4H BUSY HVA HVE SV OI 70 0111 0000 Program Flash control Write E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 FMDATA Program Flash data E5H 00 0000 0000 I2ADR I2C slave address register DBH I2ADR 6 I2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 Bit address DF DE DD DC DB DA D9 D8 I2CON I2C control regi...

Page 13: ... PS PSR PT1 PX1 PT0 PX0 00 1 x000 0000 IP0H Interrupt priority 0 high B7H PWDRT H PBOH PSH PSRH PT1H PX1H PT0H PX0H 00 1 x000 0000 Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PADEE PST PCCU PSPI PC PKBI PI2C 00 1 00x0 0000 IP1H Interrupt priority 1 high F7H PADEEH PSTH PCCUH PSPIH PCH PKBIH PI2CH 00 1 00x0 0000 IP2 Interrupt priority 2 D6H PADC 00 1 00x0 0000 IP2H Interrupt pr...

Page 14: ... 1 P0M1 0 FF 1 1111 1111 P0M2 Port 0 output mode 2 85H P0M2 7 P0M2 6 P0M2 5 P0M2 4 P0M2 3 P0M2 2 P0M2 1 P0M2 0 00 1 0000 0000 P1M1 Port 1 output mode 1 91H P1M1 7 P1M1 6 P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3 1 11x1 xx11 P1M2 Port 1 output mode 2 92H P1M2 7 P1M2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00 1 00x0 xx00 P2M1 Port 2 output mode 1 A4H P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 P2M1 0 ...

Page 15: ... SP Stack pointer 81H 07 0000 0111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPR0 04 0000 0100 SPSTAT SPI status register E1H SPIF WCOL 00 00xx xxxx SPDAT SPI data register E3H 00 0000 0000 TAMOD Timer 0 and 1 auxiliary mode 8FH T1M2 T0M2 00 xxx0 xxx0 Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00 0000 0000 TCR20 CCU co...

Page 16: ...WDRUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF 5 On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 6 The only reset source that affects these SFRs is power on reset TL2 CCU timer low CCH 00 0000 0000 TMOD Timer 0 and 1 ...

Page 17: ...LSB FFFEh AD0DAT0 7 0 00 0000 0000 AD0DAT0L ADC0 data register 0 left MSB FFFFh AD0DAT0 9 2 00 0000 0000 AD0DAT1R ADC0 data register 1 right LSB FFFCh AD0DAT1 7 0 00 0000 0000 AD0DAT1L ADC0 data register 1 left MSB FFFDh AD0DAT1 9 2 00 0000 0000 AD0DAT2R ADC0 data register 2 right LSB FFFAh AD0DAT2 7 0 00 0000 0000 AD0DAT2L ADC0 data register 2 left MSB FFFBh AD0DAT2 9 2 00 0000 0000 AD0DAT3R ADC0...

Page 18: ...CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC938 has 8 kB of on chip Code memory Fig 5 P89LPC938 memory map 002aaa948 0000h 03FFh 0400h 07FFh 0800h 0BFFh 0C00h 0FFFh SECTOR 0 SECTOR 1 SECTOR 2 SECTOR 3 1000h 13FFh 1400h 17FFh 1800h 1BFFh 1C00h 1E00h 1FFFh SECTOR 4 SECTOR 5 SECTOR 6 FFEFh FF00h IAP entry points SECTOR 7 ISP CODE 512B S...

Page 19: ...rom high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator an oscillator using an external crystal or an external clock source The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz 2 2 2 Low speed oscillator option This opt...

Page 20: ... reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 Note the initial value is better than 1 please refer to the P89LPC938 data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator fre...

Page 21: ... operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage Note The oscillator must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be re...

Page 22: ...at can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution 2 9 Low powe...

Page 23: ...r Power down mode 3 2 1 A D operating modes 3 2 1 1 Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register pair which corresponds to the selected input channel see Table 7 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the...

Page 24: ...conversion mode The channels are converted from LSB to MSB order in ADINS This mode is selected by setting the SCAN0 bit in the ADMODA register 3 2 1 4 Auto scan continuous conversion mode Any combination of the eight input channels can be selected for conversion by setting a channel s respective bit in the ADINS register A conversion of each selected input will be performed and the result placed ...

Page 25: ...ble This mode is selected by setting the SCC0 bit in the ADMODA register 3 2 1 6 Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the eight input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed i...

Page 26: ...M0 bit in ADCON0 if the conversion was started in Timer triggered mode Prior to resuming conversions the user will need to reset the input multiplexer to the first user specified channel This can be accomplished by writing the ADINS register with the desired channels 3 2 5 Boundary limits interrupt The A D converter has both a high and low boundary limit register The user may select whether an int...

Page 27: ...wer down Otherwise the pin will remain 5V tolerant Please refer to the P89LPC938 data sheet for specifications 3 2 8 Power down and Idle mode In Idle mode the A D converter if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total Power down mode the A D does not function If the A D i...

Page 28: ...Reserved 4 SCAN0 When 1 selects single conversion mode auto scan or fixed channel 5 SCC0 When 1 selects fixed and dual channel continuous conversion modes 6 BURST0 When 1 selects auto scan continuous conversion mode 7 BNDI0 ADC0 boundary interrupt flag When set indicates that the converted result is inside outside of the range defined by the ADC0 boundary registers Table 15 A D Mode register B ADM...

Page 29: ...e 17 A D Input select ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN07 AIN06 AIN05 AIN04 AIN03 AIN02 AIN01 AIN00 Reset 0 0 0 0 0 0 0 0 Table 18 A D Input select ADINS address A3h bit description Bit Symbol Description 0 AIN00 When set enables the AD00 pin for sampling and conversion 1 AIN01 When set enables the AD01 pin for sampling and conversion 2 AIN02 When set enables the AD02...

Page 30: ...rizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Table 20 Boundary status register 0 BNDSTA0 address FFEDh bit description Bit Symbol Description 0 BST00 When set indicates that conversion result for the AD00 pin was inside outside the boundary limits This bit is cleared in sof...

Page 31: ... has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested i...

Page 32: ...1Bh ET1 IEN0 3 IP0H 3 IP0 3 10 No Serial port Tx and Rx TI and RI 0023h ES ESR IEN0 4 IP0H 4 IP0 4 13 No Serial port Rx RI Brownout detect BOF 002Bh EBO IEN0 5 IP0H 5 IP0 5 2 Yes Watchdog timer Real time clock WDOVF RTCF 0053h EWDRT IEN0 6 IP0H 6 IP0 6 3 Yes I2C interrupt SI 0033h EI2C IEN1 0 IP0H 0 IP0 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IP0H 0 IP0 0 8 Yes Comparators 1 and 2 interrupts C...

Page 33: ...Table 23 1 See Section 10 Capture Compare Unit CCU Fig 9 Interrupt sources interrupt enables and power down wake up sources 002aab104 IE0 EX0 IE1 EX1 BOF EBO KBIF EKBI interrupt to CPU wake up if in power down EWDRT CMF2 CMF1 EC EA IE0 7 TF1 ET1 TI RI RI ES ESR TI EST SI EI2C SPIF ESPI RTCF ERTC RTCCON 1 WDOVF TF0 ET0 any CCU interrupt 1 ECCU EEIF EADC EIEE ENADCI0 ADCI0 ENBI1 BNDI1 Table 23 Numbe...

Page 34: ...ctional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also a...

Page 35: ...mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC938 data sheet Dynamic characteristics for glitch filter specifications 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contai...

Page 36: ...iguration has the same pull down structure as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 13 A push pull port pin has a Schmitt triggered input that also has a glitch...

Page 37: ...their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PT0AD bits 1 through 5 default to logic 0s to enable the digital functions 5 7 Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices After power up all I O pins except P1 5 may be configured by software Pin P1 ...

Page 38: ...able 25 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P0 0 P0M1 0 P0M2 0 KBIO CMP2 AD05 P0 1 P0M1 1 P0M2 1 KBI1 CIN2B AD00 Refer to Section 5 6 Port 0 and Analog Comparator functions for usage as analog inputs P0 2 P0M1 2 P0M2 2 KBI2 CIN2A AD01 P0 3 P0M1 3 P0M2 3 KBI3 CIN1B AD02 P0 4 P0M1 4 P0M2 4 KBI4 CIN1A AD03 P0 5 P0M1 5 P0M2 5 KBI5 CMPREF P0 6 P...

Page 39: ... Detection is enabled the brownout condition occurs when VDD falls below the Brownout trip voltage VBO see P89LPC938 data sheet Static characteristics and is negated when VDD rises above VBO If the P89LPC938 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may pr...

Page 40: ...FG1 5 PMOD1 PMOD0 PCON 1 0 BOPD PCON 5 BOI PCON 4 EBO IEN0 5 EA IEN0 7 Description 0 erased XX X X X X Brownout disabled VDD operating range is 2 4 V to 3 6 V 1 program med 11 total power down X X X X 11 any mode other than total power down 1 brownout detect power down X X X Brownout disabled VDD operating range is 2 4 V to 3 6 V However BOPD is default to logic 0 upon power up 0 brownout detect a...

Page 41: ...it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 256 clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increas...

Page 42: ... for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 11 Table 30 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD DEEPD VCPD ADPD I2...

Page 43: ...system power is removed VDD will fall below the minimum specified operating voltage When using an oscillator frequency above 12 MHz in some applications an external brownout detect circuit may be required to hold the device in reset when VDD falls below the minimum specified operating voltage Reset can be triggered from the following sources see Figure 14 External reset pin during power on or if u...

Page 44: ... reset If RST is still asserted after the Power on reset is over R_EX will be set 1 R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 R_WD Watchdog Timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 3 R_BK break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a sys...

Page 45: ...in which the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter...

Page 46: ...is enabled when the TR1 control bit is set Table 35 Timer Counter Mode register TMOD address 89h bit description continued Bit Symbol Description Table 36 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 T0M2 Reset x x x 0 x x x 0 Table 37 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 T0M2 Mode...

Page 47: ...parate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 18 TL0 uses the Timer 0 control bits T0C T T0GATE TR0 INT0 and TF0 TH0 is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus TH0 now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC938...

Page 48: ...ardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software 4 TR0 Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TF0 Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in ...

Page 49: ... 0 or 1 in Mode 2 8 bit auto reload 002aaa921 PCLK Tn pin TRn Gate INTn pin C T 0 C T 1 TLn 8 bits THn 8 bits TFn control ENTn Tn pin toggle overflow interrupt reload Fig 18 Timer counter 0 Mode 3 two 8 bit counters 002aaa922 PCLK Osc 2 T0 pin TR0 TR1 Gate INT0 pin C T 0 C T 1 TL0 8 bits TF0 control ENT0 AUXR1 4 T0 pin P1 2 open drain toggle overflow interrupt TH0 8 bits TF1 control ENT1 AUXR1 5 T...

Page 50: ...2 oscillator is used as the CPU clock then the RTC will use CCLK as its clock source regardless of the state of the RTCS1 0 in the RTCCON register There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON ...

Page 51: ... be cleared before updating RTCS1 RTCS0 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IEN0 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device 9 4 Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associat...

Page 52: ...rnal RC oscillator 100 0 00 High frequency crystal Watchdog oscillator DIVM 01 Medium frequency crystal 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 x xx undefined undefined 110 x xx undefined undefined 111 0 00 External clock input External clock input DIVM...

Page 53: ...ck Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt...

Page 54: ...by setting the CCU Mode Select bits TMOD21 and TMOD20 in the CCU Control Register 0 TCR20 as shown in the table in the TCR20 register description Table 47 The CCU direction control bit TDIR2 determines the direction of the count TDIR2 0 Count up TDIR2 1 Count down If the timer counting direction is changed while the counter is running the count sequence will be reversed in the CCUCLK cycle followi...

Page 55: ... as the latch is pending TCOU2 will read as one and will return to zero when the latching takes place TCOU2 also controls the latching of the Output Compare registers OCR2A OCR2B and OCR2C When writing to timer high byte TH2 the value written is stored in a shadow register When TL2 is written the contents of TH2 s shadow register is transferred to TH2 at the same time that TL2 gets updated Thus TH...

Page 56: ...TPCR2L 7 Prescaler bit 7 Table 47 CCU control register 0 TCR20 address C8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 Reset 0 0 0 0 0 0 0 0 Table 48 CCU control register 0 TCR20 address C8h bit description Bit Symbol Description 1 2 TMOD20 21 CCU Timer mode TMOD21 TMOD20 00 Timer is stopped 01 Basic timer function 10 Asymmetrical PWM uses PLL as clo...

Page 57: ...s set up by OCMx1 OCMx0 without causing an interrupt In basic timer operating mode the FCOx bits always read zero Note This bit has a different function in PWM mode When an output compare pin is enabled and connected to the compare latch the state of the compare pin remains unchanged until a compare event or forced compare occurs When the user writes to change the output compare value the values w...

Page 58: ... Filter ICNFx bit is set the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event The inputs are sampled every two CCLK periods regardless of the speed of the timer An event counter can be set to delay a capture by a number of capture events The three bits ICECx2 ICECx1 and ICECx0 in the CCCRx register determine the number of edges ...

Page 59: ...module which in PWM mode is used for PWM waveform generation Table 52 shows the behavior of the compare pins in PWM mode The user will have to configure the output compare pins as outputs in order to enable the PWM output As with basic timer operation when the PWM compare pins are connected to the compare logic their logic state remains unchanged However since the bit FCO is used to hold the halt ...

Page 60: ...gated on every counter cycle This is shown in the following figure 1 x A B C D 2 ON means in the CCUCLK cycle after the event takes place Fig 24 Alternate output mode Table 52 Output compare pin behavior OCMx1 1 OCMx0 1 Output Compare pin behavior Basic timer mode Asymmetrical PWM Symmetrical PWM 0 0 Output compare disabled On power on this is the default state and pins are configured as inputs 0 ...

Page 61: ...rupt will still operate as normal even if it has this added functionality enabled When the PWM unit is halted the timer will still run as normal The HLTRN bit in TCR20 will be set to indicate that a halt took place In order to re activate the PWM the user must clear the HLTRN bit The user can force the PWM unit into halt by writing a logic 1 to HLTRN bit 10 10 PLL operation The PWM module features...

Page 62: ...e CCU timer overflow captured input events on Input Capture blocks A B and compare match events on Output Compare blocks A through D One common interrupt vector is used for the CCU service routine and interrupts can occur simultaneously in system usage To resolve this situation a priority encode function of the seven interrupt bits in TIFR2 SFR is implemented after each bit is AND ed with the corr...

Page 63: ... and a return from interrupt can occur Otherwise return to step 2 for the next interrupt Fig 25 Capture compare unit interrupts 002aaa896 interrupt to CPU TOIE2 TICR2 7 TOIF2 TIFR2 7 TICIE2A TICR2 0 TICF2A TIFR2 0 TICIE2B TICR2 1 TICF2B TIFR2 1 TOCIE2A TICR2 3 TOCF2A TIFR2 3 TOCIE2B TICR2 4 TOCF2B TIFR2 4 TOCIE2C TICR2 5 TOCF2C TIFR2 5 TOCIE2D TICR2 6 TOCF2D TIFR2 6 EA IEN0 7 ECCU IEN1 4 PRIORITY ...

Page 64: ...rupt Flag Bit Set by hardware when an input capture event is detected Cleared by software 2 Reserved for future use Should not be set to logic 1 by user program 3 TOCF2A Output Compare Channel A Interrupt Flag Bit Set by hardware when the contents of TH2 TL2 match that of OCRHA OCRLA Compare channel A must be enabled in order to generate this interrupt If EA bit in IEN0 ECCU bit in IEN1 and TOCIE2...

Page 65: ... 1 0 Symbol TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B TICIE2A Reset 0 0 0 0 0 x 0 0 Table 60 CCU interrupt control register TICR2 address C9h bit description Bit Symbol Description 0 TICIE2A Input Capture Channel A Interrupt Enable Bit If EA bit and this bit all be set when a capture event is detected the program counter will vectored to the corresponding interrupt 1 TICIE2B Input Capture Chan...

Page 66: ...w rate or the Baud Rate Generator see Section 11 6 Baud Rate generator and selection on page 66 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 11 5 SFR space The UART SFRs are at the following location...

Page 67: ...rogrammed when SMOD0 is logic 0 Table 62 UART baud rate generation SCON 7 SM0 SCON 6 SM1 PCON 7 SMOD1 BRGCON 1 SBRGS Receive transmit baud rate for UART 0 0 X X CCLK 16 0 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGR0 16 1 0 0 X CCLK 32 1 X CCLK 16 1 1 0 0 CCLK 256 TH1 64 1 0 CCLK 256 TH1 32 X 1 CCLK BRGR1 BRGR0 16 Table 63 Baud Rate Generator Control register BRGCON address BDh bi...

Page 68: ...by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by softwa...

Page 69: ...w Cleared by software 3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character writt...

Page 70: ... back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or...

Page 71: ...received 9th data bit goes into RB8 and the first 8 data bits go into SBUF 11 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table Fig 28 Serial Port Mode 1 only single transmit buffering case is shown transmit start bit stop bit INTLO 0 TX clock write to SBUF shift TXD TI D0 D1 D5 D2 D6 D3 D4 D7 receive RX clock shift RI start b...

Page 72: ...buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out 11 16 Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 11 17 Transmit interrupts with double...

Page 73: ...ded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 11 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after...

Page 74: ...a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 11 19 Multiprocessor communications UART mo...

Page 75: ...hile excluding others The following examples will help to show the versatility of this scheme In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique addre...

Page 76: ...l transfer The I2C bus may be used for test and diagnostic purposes A typical I2C bus configuration is shown in Figure 31 Depending on the state of the direction bit R W two types of data transfers are possible on the I2C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave return...

Page 77: ...ed data is located at the MSB of I2DAT 12 2 I2C slave address register I2ADR register is readable and writable and is only used when the I2C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Fig 31 I2C bus configuration OTHER DEVICE WITH I2C BUS INTERFACE SDA SCL RP RP OTHER...

Page 78: ... STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I2C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 76 I2C Control register I2CON address D8h bit allocatio...

Page 79: ...a STOP condition is transmitted to the I2C bus When the bus detects the STOP condition it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware au...

Page 80: ...N must be set to 1 to enable the I2C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 Table 80 I2C clock rates selection Bit data rate Kbit sec at fosc I2SCLL I2SCLH CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz...

Page 81: ...wledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or 0B0h if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 83 12 6 2 Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started i...

Page 82: ...wed by the data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 86 for the status codes and actions Fig 33 Format of Master Receiver mode S R A slave address logic 0 write logic 1 read from Master...

Page 83: ...pt is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer Fig 35 Format of Slave Receiver mode S...

Page 84: ...m INTERNAL BUS 002aaa899 ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 I2ADR ACK BIT COUNTER ARBITRATION SYNC LOGIC 8 I2DAT TIMING AND CONTROL LOGIC SERIAL CLOCK GENERATOR CCLK interrupt INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE P1 3 P1 3 SDA P1 2 SCL P1 2 timer 1 overflow CONTROL REGISTERS SCL DUTY CYCLE REGISTERS I2CON I2SCLH I2SCLL 8 STATUS DECODER status bus STATUS REGISTER 8 I2STAT ...

Page 85: ...ed no I2DAT action or 0 1 0 x STOP condition will be transmitted STO flag will be reset no I2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been transmitted NOT ACK has been received Load data byte or 0 0 0 x Data byte will be transmitted ACK bit will be received no I2DAT action or 1 0 0 x Repeated START will be transmitted ...

Page 86: ...Master Receiver mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI STA 08H A START condition has been transmitted Load SLA R x 0 0 x SLA R will be transmitted ACK bit will be received 10H A repeat START condition has been transmitted Load SLA R or x 0 0 x As above Load SLA W SLA W will be transmitted ...

Page 87: ...to I2CON STA STO SI AA 60H Own SLA W has been received ACK has been received no I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned no I2DAT action x 0 0 1 Data byte will be received and ACK will be returned 68H Arbitration lost in SLA R Was master Own SLA W has been received ACK returned No I2DAT action or x 0 0 0 Data byte will be received and NOT ACK will be returned...

Page 88: ...call Data has been received ACK has been returned Read data byte or x 0 0 0 Data byte will be received and NOT ACK will be returned read data byte x 0 0 1 Data byte will be received and ACK will be returned 98H Previously addressed with General call Data has been received NACK has been returned Read data byte 0 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call addr...

Page 89: ...he bus becomes free Table 85 Slave Receiver mode continued Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA Table 86 Slave Transmitter mode Status code I2STAT Status of the I2C hardware Application software response Next action taken by I2C hardware to from I2DAT to I2CON STA STO SI AA A8h Own SLA R h...

Page 90: ...ndition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free C8H Last data byte in I2DAT has been transmitted AA 0 ACK has been received No I2DAT action or 0 0 0 0 Switched to not addressed SLA ...

Page 91: ...tem is disabled i e SPEN SPCTL 6 0 reset value If the SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits If the SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is con...

Page 92: ... LSB of the data word is transmitted first 0 The MSB of the data word is transmitted first 6 SPEN SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore 1 MSTR bit 4 decides whether the device is a master or slave 0 The SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 92 Table 89 SPI Status regist...

Page 93: ...2 4 SS configured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 13 4 Mode change on SS to slave Table 91 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MSB LSB Reset 0 0 0 0 0 0 0 0 Fig 39 SPI single master single slave configuration Fig 40 SPI d...

Page 94: ...r slave 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR 8 BIT SHIFT REGISTER MISO MOSI SPICLK port port MISO MOSI SPICLK SS slave 8 BIT SHIFT REGISTER MISO MOSI SPICLK SS Table 92 SPI master and slave selection SPEN SSIG SS Pin MSTR Master or Slave Mode MISO MOSI SPICLK Remarks 0 x P2 4 1 x SPI Disabled P2 3 1 P2 2 1 P2 5 1 SPI disabled P2 2 P2 3 P2 4 P2 5 are used as port pins 1 0 0 0 Slave output input...

Page 95: ...g device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt...

Page 96: ... bit is set to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The sl...

Page 97: ...iconductors UM10119 P89LPC938 User manual 1 Not defined Fig 42 SPI slave transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 1 002aaa934 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 ...

Page 98: ...iconductors UM10119 P89LPC938 User manual 1 Not defined Fig 43 SPI slave transfer format with CPHA 1 1 2 3 4 5 6 7 8 MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa935 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 1 ...

Page 99: ...iconductors UM10119 P89LPC938 User manual 1 Not defined Fig 44 SPI master transfer format with CPHA 0 1 2 3 4 5 6 7 8 MSB LSB 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB MSB LSB DORD 0 DORD 1 6 1 5 2 4 3 3 4 2 5 1 6 LSB MSB 002aaa936 Clock cycle SPICLK CPOL 0 SPICLK CPOL 1 MOSI input MISO output SS if SSIG bit 0 DORD 0 DORD 1 ...

Page 100: ...m a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 14 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 94 The overall connections to both comparators are shown in Figure...

Page 101: ... a hardware interrupt if enabled Cleared by software 1 COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected ...

Page 102: ...ator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user...

Page 103: ...e input on CIN1A Negative input from CMPREF pin Output to CMP1 pin enabled CALL delay10us The comparator needs at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF1 in this case befo...

Page 104: ...not equal then any key connected to Port0 which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use...

Page 105: ...to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 16 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IEN0 6 if ...

Page 106: ...he processor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable 16 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 49 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded t...

Page 107: ...If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a ...

Page 108: ...hdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set t...

Page 109: ...the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock s...

Page 110: ...re When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode Fig 49 Watchdog Timer in Watchdog Mode WDTE 1 PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON A7H SHADOW REGISTER PRESCALER 002aa...

Page 111: ...1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 106 Table 105 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENT0 SRST 0 DPS Reset 0 0 0 0 0 0 x 0 Table 106 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not ...

Page 112: ...OVX A DPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC938 since the part does not have an external data b...

Page 113: ... an interrupt request The EEIF bit will need to be cleared by software 18 1 Data EEPROM read A byte can be read via polling or interrupt 1 Write to DEECON with ECTL1 ECTL0 DEECON 5 4 00 and correct bit 8 address to EADR8 Note that if the correct values are already written to DEECON there is no need to write to this register 2 Without writing to the DEEDAT register write address bits 7 to 0 to DEEA...

Page 114: ...will automatically set off a write if DEECON 5 4 00 the user must take great caution in a write to the DEEDAT register It is strongly recommended that the user disables interrupts prior to a write to the DEEDAT register and enable interrupts after all writes are over An example is as follows CLR EA disable interrupt MOV DEEDAT R0 write data pattern MOV DEEADR R1 write address for the data SETB EA ...

Page 115: ...c 1s wait for the Data EEPROM interrupt then read poll the EEIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled and only polling is enabled When EEIF is logic 1 the operation is complete 19 Flash memory 19 1 General description The P89LPC938 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The ...

Page 116: ... factory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port 19 4 Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable f...

Page 117: ... for the cycle If an interrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the OI flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user ...

Page 118: ... R HVA HVE SV OI Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 Reset 0 0 0 0 0 0 0 0 Table 110 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 OI R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or ...

Page 119: ... ANL A 0FH save only four lower bits JNZ BAD CLR C clear error flag if good RET and return BAD SETB C set error flag RET and return A C language routine to load the page register and perform an erase program operation is shown below include REG938 H unsigned char idata dbytes 64 data buffer unsigned char Fm_stat status result bit PGM_USER unsigned char unsigned char bit prog_fail void main prog_fa...

Page 120: ...s of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user application 19 7 Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash prog...

Page 121: ...y pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to...

Page 122: ...lf In the Intel Hex record the NN represents the number of data bytes in the record The P89LPC938 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file ma...

Page 123: ...02030405006070809cc 01 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001cc 02 Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field but value is a don t care ss subfunction code dd data cc checksum Subfunction codes 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Securit...

Page 124: ...e 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 10 Manufacturer Id 11 Device Id 12 Derivative Id Example 0100000312cc 04 Erase Sector Page 03xxxx04ssaaaacc Where xxxx required field but value is a don t care aaaa sector page address ss 01 erase s...

Page 125: ... s registers before making a call to PGM_MTP at FF03H The IAP calls are shown in Table 114 05 Read Sector CRC 01xxxx05aacc Where xxxx required field but value is a don t care aa sector address high byte cc checksum Example 0100000504F6cc 06 Read Global CRC 00xxxx06cc Where xxxx required field but value is a don t care cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where ...

Page 126: ...and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 BOOTVEC and BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit...

Page 127: ...tion resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 113 If the application permits in...

Page 128: ...e IDATA Return parameter s R7 status Carry set on error clear on no error Read Version Id Input parameters ACC 01h Return parameter s R7 IAP code version id Misc Write requires key Input parameters ACC 02h R5 data to write R7 register address 00 UCFG1 01 reserved 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 0A Security Byte 2 0...

Page 129: ...te 0 09 Security Byte 1 0A Security Byte 2 0B Security Byte 3 0C Security Byte 4 0D Security Byte 5 0E Security Byte 6 0F Security Byte 7 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page requires key Input parameters ACC 04h R7 00H erase page or 01H erase sector R4 sector page address MSB R5 sector page address LSB Return para...

Page 130: ...ar on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 07h R4 address MSB R5 address LSB Return parameter s R7 data Table 114 IAP function calls continued IAP function IAP call parameters Table 115 Fla...

Page 131: ...Byte UCFG1 bit description continued Bit Symbol Description Table 117 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 20 30 tolerance 011 Internal RC oscillator 7 373 MHz 2 5 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MH...

Page 132: ...r program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed Table 121 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0 Factory default value 0 0 0 1 1 1 1 1 Table 122 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address ...

Page 133: ...1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA 7 DCCP Disable Clear Configuration Protection command If Programmed to 1 the Clear Configuration Protection CCP comm...

Page 134: ...th borrow 1 1 96 to 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to 0F INC dir Increment direct byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data po...

Page 135: ...to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect m...

Page 136: ...outine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and cl...

Page 137: ...n and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warra...

Page 138: ...nterrupt 26 3 2 6 Clock divider 27 3 2 7 I O pins used with ADC functions 27 3 2 8 Power down and Idle mode 27 4 Interrupts 30 4 1 Interrupt priority structure 31 4 2 External Interrupt pin glitch suppression 31 5 I O ports 33 5 1 Port configurations 34 5 2 Quasi bidirectional output configuration 34 5 3 Open drain output configuration 35 5 4 Input only configuration 36 5 5 Push pull output config...

Page 139: ...ter 95 13 4 Mode change on SS 95 13 5 Write collision 96 13 6 Data mode 96 13 7 SPI clock prescaler select 100 14 Analog comparators 100 14 1 Comparator configuration 100 14 2 Internal reference voltage 102 14 3 Comparator input pins 102 14 4 Comparator interrupt 102 14 5 Comparators and power reduction modes 102 14 6 Comparators configuration example 103 15 Keypad interrupt KBI 104 16 Watchdog ti...

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