© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 03 — 7 June 2005
19 of 139
Philips Semiconductors
UM10119
P89LPC938 User manual
2.
Clocks
2.1 Enhanced CPU
The P89LPC938 uses an enhanced 80C51 CPU which runs at six times the speed of
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most
instructions execute in one or two machine cycles.
2.2 Clock definitions
The P89LPC938 device has several internal clocks as defined below:
OSCCLK —
Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources and can also be optionally divided to a slower frequency (see
and
Section 2.8 “CPU Clock (CCLK) modification: DIVM register”
Note:
f
osc
is defined as the
OSCCLK frequency.
CCLK —
CPU clock; output of the DIVM clock divider. There are two CCLK cycles per
machine cycle, and most instructions are executed in one to two machine cycles (two or
four CCLK cycles).
RCCLK —
The internal 7.373 MHz RC oscillator output.
PCLK —
Clock for the various peripheral devices and is
CCLK
⁄
2
.
2.2.1 Oscillator Clock (OSCCLK)
The P89LPC938 provides several user-selectable oscillator options. This allows
optimization for a range of needs from high precision to lowest possible cost. These
options are configured when the FLASH is programmed and include an on-chip watchdog
oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external
clock source. The crystal oscillator can be optimized for low, medium, or high frequency
crystals covering a range from 20 kHz to 18 MHz.
2.2.2 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
2.2.3 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
2.2.4 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
When using an oscillator frequency
above 12 MHz, the reset input function of P1.5 must be enabled. An external circuit
is required to hold the device in reset at power-up until V
DD
has reached its
specified level. When system power is removed V
DD
will fall below the minimum
specified operating voltage. When using an oscillator frequency above 12 MHz, in
some applications, an external brownout detect circuit may be required to hold the
device in reset when V
DD
falls below the minimum specified operating voltage.
