EN 70
3139 785 30981
8.
Circuit- and IC Description
PIN
DESCRIPTION
T
ERM
INA
L
I
/
O
DESCR
I
P
TION
NA
ME
N
UMBER
I
/
O
DESCR
I
P
TION
A
nal
o
g
Video
VI_
1
_A
VI_
1
_B
VI_
1
_C
VI_2_A
VI_2_B
VI_2_C
VI_
3
_A
VI_
3
_B
VI_
3
_C
VI_
4
_A
80
1
2
7
8
9
16
17
18
2
3
I
VI_
1
_
x:
A
nal
o
g vide
o
inpu
t
f
or
CVBS/Pb/B/C
VI_2_
x:
A
nal
o
g vide
o
inpu
t
f
or
CVBS/Y/
G
VI_
3
_
x:
A
nal
o
g vide
o
inpu
t
f
or
CVBS/Pr/R/C
VI_
4
_A
:
A
nal
o
g vide
o
inpu
t
f
or
CVBS/Y
U
p
to
10 c
o
mp
o
si
t
e, 4
S-
vide
o
, and
2
c
o
mp
o
si
t
e
or
3 c
o
mp
o
nen
t
vide
o
inpu
t
s (
or
a c
o
m
b
ina
t
i
o
n
t
he
r
e
o
f)
can
b
e supp
ort
ed.
T
he inpu
t
s mus
t
b
e ac
-
c
o
upled.
T
he
r
ec
o
mmended c
o
upling capaci
tor
is 0.1
μ
F
.
T
he p
o
ssi
b
le inpu
t
c
o
nfigu
r
a
t
i
o
ns a
r
e lis
t
ed in
t
he inpu
t
selec
t
r
egis
t
e
r
a
t
I2C
su
b
add
r
ess 00h (see
S
ec
t
i
o
n
2
.11.1).
Cl
o
ck S
i
gnals
DATAC
LK
40
O
Line
-
l
o
cked da
t
a
o
u
t
pu
t
cl
o
ck.
XTA
L1
74
I
E
x
t
e
r
nal cl
o
ck
r
efe
r
ence inpu
t
.
It
may
b
e c
o
nnec
t
ed
to
an ex
t
e
r
nal
o
scilla
tor
wi
t
h a 1.8
-V
c
o
mpa
t
i
b
le cl
o
ck
signal
or
a 14.31818
-
MHz c
r
ys
t
al
o
scilla
tor
.
XTA
L
2
75
O
E
x
t
e
r
nal cl
o
ck
r
efe
r
ence
o
u
t
pu
t
.
Not
c
o
nnec
t
ed if
XTA
L1 is d
r
iven
b
y an ex
t
e
r
nal single
-
ended
o
scilla
tor
.
D
i
g
i
tal
Video
C
[9:0]
/
G
PIO
[9:0]
57, 58,
59, 60,
63, 64,
65, 66,
69, 70
O
D
igi
t
al vide
o
o
u
t
pu
t
o
f
CbCr
,
C
[9] is M
SB
and
C
[0] is L
SB
.
U
nused
o
u
t
pu
t
s can
b
e lef
t
unc
o
nnec
t
ed.
A
ls
o
,
t
hese
t
e
r
minals can
b
e p
ro
g
r
amma
b
le gene
r
al
-
pu
r
p
o
se
I/O
.
For
t
he 8
-b
i
t
m
o
de,
t
he
t
w
o
L
SB
s a
r
e ign
or
ed.
D_B
L
UE
58
I
D
igi
t
al
B
L
UE
inpu
t
f
ro
m
o
ve
r
lay device
D_
G
REEN
59
I
D
igi
t
al G
REEN
inpu
t
f
ro
m
o
ve
r
lay device
D_RED
60
I
D
igi
t
al
RED
inpu
t
f
ro
m
o
ve
r
lay device
FSO
57
I
F
as
t-
swi
t
ch
o
ve
r
lay
b
e
t
ween digi
t
al
R
G
B
and any vide
o
Y
[9:0]
43, 44,
45, 46,
47, 50,
51, 5
2
,
53, 54
O
D
igi
t
al vide
o
o
u
t
pu
t
o
f
Y/YCbCr
,
Y
[9] is M
SB
and
Y
[0] is L
SB
.
For
t
he 8
-b
i
t
m
o
de,
t
he
t
w
o
L
SB
s a
r
e ign
or
ed.
U
nused
o
u
t
pu
t
s can
b
e lef
t
unc
o
nnec
t
ed.
M
i
sc
e
llan
eo
us S
i
gnals
FSS/
G
PIO
35
I/O
F
as
t-
swi
t
ch (
b
lanking) inpu
t
.
S
wi
t
ching signal
b
e
t
ween
t
he synch
ro
n
o
us c
o
mp
o
nen
t
vide
o
(
YPbPr/R
G
B
)
and
t
he c
o
mp
o
si
t
e vide
o
inpu
t
.
Pro
g
r
amma
b
le gene
r
al
-
pu
r
p
o
se
I/O
GL
CO/I2CA
37
I/O
Genl
o
ck c
o
n
tro
l
o
u
t
pu
t
(GL
CO
).
T
w
o
Genl
o
ck da
t
a f
or
ma
t
s a
r
e availa
b
le:
TI
f
or
ma
t
and
r
eal
t
ime c
o
n
tro
l
(
RTC
) f
or
ma
t
.
D
u
r
ing
r
ese
t
,
t
his
t
e
r
minal is an inpu
t
used
to
p
ro
g
r
am
t
he
I2C
add
r
ess L
SB
.
INTRE
Q
30
O
I
n
t
e
rr
up
t
r
eques
t
PWDN
33
I
Po
we
r
d
o
wn inpu
t
:
1 =
Po
we
r
d
o
wn
0 =
Nor
mal m
o
de
RESETB
34
I
R
ese
t
inpu
t
, ac
t
ive l
o
w