Block Diagrams
9.
Block Diagram Control & Clock Signals
C CLOCK
S
IGNAL
S
B09E
IR LED
B09D
FPGA 10
8
0P: I/O BANK
S
B09C
FPGA 10
8
0P: POW + CONTR
B0
8
A
U
S
B 2.0
B0
8
B
U
S
B 2.0
B0
3
D
PNX
8
541: CONTROL
B09A
S
UPPLY
T01A
CHANNEL DECODER
T01B
MAIN TUNER
B0
3
E
PNX
8
5xx:
S
DRAM
B0
3
D
PNX
8
5xx: CONTROL
B0
3
C
PNX
8
5xx: CONTROL
B06C
HDMI
S
WITCH
B0
3
B
PNX
8
5xx: FLA
S
H
B0
3
F
PNX
8
5xx: FLA
S
H
B10C
PACIFIC
3
B10B
PACIFIC
3
: DI
S
PLAY INTERFACING
B0
3
B
PNX
8
5xx:
S
TANDBY CONTROLLER
B12B
IBOARD
B12A
IBOARD
B0
3
PNX
8
5xx
B02A
PRO: IDIOM
B12B
IBOARD
1HF0
27M
AG2
AG1
FE-DATA(0-7)
TUN-FE-DATA
1N51
6
LED1-
3
V
3
KEYBOARD
U5
AF4
W1
AK17
DETECT-5V-12V
AA
3
AC
3
RE
S
ET-
S
Y
S
-DETECT
U1
ENABLE-
3
V
3
PNX
8
5xx
7H00
PNX
8
541E
4
3
21
U
S
B20-1-DM
U
S
B20-1-DP
U
S
B 2.0
CONNECTOR
TO IR/LED PANEL AND
KEYBOARD CONTROL
U4
RE
S
ET-NVM_WP-NANDFLA
S
H
4
AA1
LED2-
3
V
3
LED1-OUT
LED2-OUT
U
3
ENABLE-1V2
B0
3
D
CONTROL
1HF0
27M
AG2
AG1
1N
3
1
1N
3
0
3
1
4
S
TANDBY CONTROLLER
B0
3
B
W4
AV1-BLK
2
3
RC
AA2
1
LIGHT-
S
EN
S
OR
AF
3
KEYBOARD
RC
IR-o
u
t-iB
LIGHT-
S
EN
S
OR
+5V_
S
TANDBY
+12V
V5
CTRL1-
S
TBY_LAMP-ON
V4
AUDIO-RE
S
ET
AH16
DV-B
3
_AUDIO-MUTE
Y4
CTRL4-
S
TBY_
S
ELECT-PWM-ANA
Y
3
CTRL
3
-
S
TBY_POWER-OK-DI
S
P
6
S
PI-CLK
512K
FLA
S
H
7H02
M25P05-AVMN6P
AD1
3
S
PI-WP
AE4
1
S
PI-C
S
B
AE
3
5
S
PI-
S
DO
AD4
2
S
PI-
S
DI
AE1
W
3
ON-MODE
7
7N00
I
S
P1564HL
PCI
HO
S
T
CONTROLLER
U
S
B20-OC1
U
S
B20-OC2
7
8
U
S
B20-PWE1
79
U
S
B20-PWE2
88
8
7
83
8
5
U
S
B20-2-DM
U
S
B20-2-DP
90
92
PCI-CLK-U
S
B20
DV-CLK-PLL
7
5
H4
F1
8
5
RE
S
ET-
S
Y
S
-DETECT
5
3
1B2
8
1
BACKLIGHT-OUT
LAMP-ON-OUT
BACKLIGHT-BOO
S
T
7T1
8
TDA10060HL
DVB-T
CHANNEL
DECODER
FE-CLK
56
B04E
PCI-CLK-OUT
AK26
PCI-CLK-U
S
B20
PCI-CLK-PNX
8
5
3
5
B0
3
C
CONTROL
A21
PCI-CLK-PNX
8
5
3
5
RE
S
ET-
S
Y
S
-DETECT
AJ26
B0
8
A
B0
3
C
B0
8
A
IRQ-PCI
T
3
B10B
CTRL1-MIP
S
_LCD-PWR-ON
T2
B0
8
A
7HC4
7HA
3
EEPROM
(
8
Kx
8
)
7HC
3
M24C64-WDW6P
RE
S
ET-NVM_WP-NANDFLA
S
H-INV
NAND
FLA
S
H
(512Mx
8
)
7HA0
NAND512W
3
A2CN6E
19
8
B01A
V
3
UART-
S
WITCH
B0
3
B
B01A
B10B
B10B
6
S
TANDBYn
7
B01B
B01B
W2
RE
S
ET-PI
B02A
V25
S
EN
S
E+1V2-PNX
8
541
B01A
B05B
B10B
2
POWER-OK-DI
S
PLAY
B0
3
B
7HD0
NCP
3
0
3
L
S
N
2
IN
1
R
S
T
+
3
V
3
-
S
TANDBY
3
GND
B0
3
C
B0
3
E
S
DRAM
B0
3
G
VIDEO
S
TREAM
S
7J00
AD
8
197AA
S
TZ
HDMI
S
WITCH
RE
S
ET-
S
Y
S
-DETECT
44
FE-VALID
6
3
FE-
S
OP
TUN-FE-CLK
TUN-FE-VALID
TUN-FE-
S
OP
57
R11
R
8
R9
B2
H1
B
8
B9
G1
B0
8
A
B0
8
A
RE
S
ET-
S
Y
S
-DETECT
E22
PCI-REQ-U
S
B20
E20
PCI-GNT-U
S
B20
9
8
E14
J2
H16
H2
N9
B0
3
D
CONTROL
PCI-AD(24-
3
1) --> NAND-AD(0-7)
7HG0
EDE2516AC
S
E
7HG1
EDE2516AC
S
E
S
DRAM
DDR2-A(0-12)
DDR2-D(0-
3
1)
DDR2-CLK_P
DDR2-CLK_N
N2
8
C5
D5
C4
N29
M
8
N
8
TO
POWER
S
UPPLY
B0
8
A
AC2
AV2-BLK
B0
8
A
41
5
+5V_
S
TANDBY
(AUDIO)
AUDIO-MUTE
B05C
B05A
AB2
DETECT-1V2-2V5-
3
V
3
B0
3
B
AB4
CEC-HDMI
B06B
D10
HOT-PLUG
B0
3
B
B0
3
C
AD2
CTRL5-
S
TBY_BACKLIGHT-BOO
S
T
B10B
B01B
RE
S
ET-
S
TBY
3
HF4
PCI-CLK-PNX5050_CLK-MOP
B09D
3
HF5
1N01
12M
75
1
3
2
4
74
B0
3
A
POWER
B0
3
H
DIGITAL
VIDEO
OUT/LVD
S
RE
S
ET-PI
S
DM
9H01
S
DM
S
PI-PROG
AE2
AC1
9H0
3
S
PI-PROG
3
HF2
7
XIO-ACK
9
XIO-
S
EL-NAND
AUDIO
B0
3
H
DIGITAL
VIDEO
OUT/LVD
S
1T04
TD17
3
6F/FHFXP
TUNER
7T57
TDA9
8
9
8
HL
IF
PROCE
SS
ING
4-MHz
8
46
1
8
710_404_090
8
24.ep
s
090
8
25
B06B
PCI-AD(0-
3
1)
A11
B11
7N
3
0
RYC
8
620
OUTA
OUTB
B0
3
B
7GE2
T6TF4HFG
PACIFIC
3
172
6
191
1
88
194
192
19
3
512K
FLA
S
H
7GE1
M25P05-AVMN6P
3
1
5
2
BACKLIGHT-CONTROL
CONTROL
BACKLIGHT-OUT
B09A
7G5
3
16
8
B05C
RxP
3
CLK
7
CTRL4-P
3
B06B
17
8
1GE1
60M
165
164
AD
3
CTRL2-
S
TBY_BACKLIGHT-CTRL_RE
S
ET-P
3
7220
UP
S
D
3333
D
MCU
1205
24M
3
1
3
2
3
4
4
8
46
3
5
B12B
B12B
LED1-OUT
LED2-OUT
B09E
B09E
B12B
B12B
B12B
B12B
B12B
LED1-
3
V
3
LED2-
3
V
3
B0
3
B
B0
3
B
1
IR-o
u
t-iB
B09E
49
2
8
25
26
1T69
54M
20
21
1C04
7B01
LGDT1129
CONTROL
B0
3
B
POR
44
MUTE_iB
B12A
51
MPEG4_PWR
B12A
52
&
7262
7261
RC_IN_MICRO
IR_OUT
S
PI_DATA_IN
RC
PEND_IR
B09E
B12A
CONTROL
IR-IN_DATA_IN_RXD_
S
DA1
8
1250
1
2
3
4
5
6
RJ12
S
MARTPLUG
S
PI_CLK
IR-IN_DATA_IN_RXD_
S
DA1
GND
S
PI_DATA_OUT
GND
IR_OUT
625
3
1240-1
CONTR
OL
POR1
POR
TV_POR
F101
F102
POWER
ON RE
S
ET
B12B
B12B
TV-POR
40
1240
10
2
4
1C00
1T1
3
10
10
1
1
8
8
12
12
1
8
1
8
11
11
TO
S
Y
S
TEM INTERFACE
(OPTIONAL)
1
3
4
2
7F90
EP2C5F256C7N
CYCLONE II
10
8
0P
FPGA
DV-CLK
PCI-CLK-PNX5050_CLK-MOP
7FA
3
EPC
S
1
S
I
8
N
S
CD
DCLK
DATA0
6
2
N.C.