EN 152
Q552.2L LA
10.
Circuit Diagrams and PWB Layouts
2011-Jul-15
back to
div. table
SPI buffer
19112_0
3
9_11062
8
.ep
s
11062
8
S
PI
bu
ffer
B06D
B06D
2011-0
3
-09
3
2011-05-10
4
2010-12-2
3
2
3
1
3
9 12
3
6521
S
PB
SS
B TV550
2K11 4DDR BR
S
D
G
3
1
2
3
EN2
3
EN1
*
*
*
RE
S
B
u
ffer
Direct
47R
3
GE4
3
GE
3
47R
RE
S
RE
S
RE
S
9GE1
7
2
RE
S
*
9GE2
8
1
RE
S
9GE0-2
IGE1
RE
S
9GE0-1
4
IGE0
3
GE1-4
47R RE
S
5
47R
1
8
RE
S
6
3
RE
S
3
GE0-1
3
6
3
GE1-
3
47R
+
3
V
3
RE
S
3
GE0-
3
47R
3
GE2
10K
RE
S
RE
S
PDTC114EU
7GE1
100n
+
3
V
3
RE
S
2GE0
15
14
1
3
12
11
1
10
19
20
3
4
5
6
7
8
9
1
8
17
16
RE
S
74LVC245A
7GE0
2
RE
S
**
9GE0-4
5
4
PNX-
S
PI-
S
DI
BL-
S
PI-C
S
n
PNX-
S
PI-
S
DO
PNX-
S
PI-CLK
BL-
S
PI-CLK
BL-
S
PI-
S
DO
PNX-
S
PI-
S
DI
PNX-
S
PI-C
S
Bn
BL-
S
PI-
S
DI
BL-
S
PI-CLK
AMBI-
S
PI-CLK-OUT-R
PNX-
S
PI-CLK
PNX-
S
PI-
S
DO
AMBI-
S
PI-
S
DI-OUT_G1-R
BL-
S
PI-
S
DO
AMBI-
S
PI-
S
DO-OUT-R
BL-
S
PI-
S
DI
PNX-
S
PI-C
S
-BLn