Circuit Diagrams and PWB Layouts
EN 125
Q552.2L LA
10.
2011-Jul-15
back to
div. table
Tuner Brazil
19112_012_11062
8
.ep
s
11062
8
T
u
ner Br
a
zil
B01K
B01K
2011-0
3
-09
3
2011-05-10
4
2010-12-2
3
2
3
1
3
9 12
3
6521
S
PB
SS
B TV550
2K11 4DDR BR
S
D
OUT
IN
INH
BP
COM
X
X
S
EL
ADI_AI
ADQ_AI
AD_VREF
T
S
MD
TN
S
LADR
S
V
SS
DR2VDD
DR1VDD
VDD
S
AD_DVDD
AD_AVDD
PLLVDD
VDDC
PBVAL
RERR
RLOCK
R
S
EORF
S
BYTE
S
LOCK
S
RCK
S
RDT
S
T
S
FLG1
AGCCNTI
AGCCNTR
S
T
S
FLG0
S
YR
S
TN
0
1
S
CL
S
DA
FIL
AD_AV
SS
AD_DV
SS
PLLV
SS
I
O
0
1
P
N
P
N
P
N
AD_VREF
DTCLK
DTMB
S
_INFO
0
1
AGCI
CKI
S
CL
S
DA
*
*
*
To
b
e dr
a
wn ne
a
r PNX
8
5500
*
*
3
5
1
u
0
2FH2
4
2
1
33
R
3
FG6-4
4
5
7FE
3
LD
3
9
8
5M25
AGND
10n
2FH
8
3
FE5
1
8
K
33
R
3
FG6-2
2
7
2FH4
1
u
0
100n
2FE4
2FE
3
100n
1
u
0
2FF1
2FE5
100n
100n
2FF0
1
u
0
2FE
8
AGND
5FE5
3
0R
2FE0
1
u
0
1
8
3
2
5FE0
3
0R
4
15
33
3
7
44
47
50
57
62
19
1
41
16
3
6
56
6
3
1
3
3
5
49
64
5
52
61
60
51
38
42
8
12
14
5
8
20
17
5
3
54
55
59
45
46
6
24
9
10
7
11
3
4
4
8
4
3
3
9
40
21
29
3
0
27
2
8
22
2
3
3
2
3
1
26
25
7FE0
TC90517FG
Φ
DFE
8
DFE7
33
R
3
FG6-
3
3
6
DFE6
AGND
AGND
2FH5
1n5
1
8
p
2FG
3
AGND
4
1
3
2FG2
1
8
p
25M4
1FE0
2
33
R
3
FG7
DFE9
DFF2
DFF1
9F2
8
9F27-2
2
7
9F27-4
4
5
100n
2FH6
2FG9
100n
2FG
8
100n
2FG6
10n
10n
2FG4
100n
2FG7
AGND
AGND
10K
3
FE7
3
FE6
10K
AGND
AGND
AGND
2FH7
100n
IF49
BFE
3
IF29
BFE2
IF1
8
1
u
0
2FF9
IF17
100n
2FF
8
100n
2FF2
2FF
3
100n
100n
2FF4
2FF6
1
u
0
2FF5
100n
5FE4
3
0R
IF6
8
IF69
AGND
IF66
1
u
0
2FE6
3
0R
5FE
3
1
8
9F27-1
2FG1
1
u
0
100n
2FG0
5FE
8
3
0R
2FF7
100n
AGND
5FG2
3
0R
100R
3
FE9
3
FE
8
100R
IF64
IF65
IF6
3
IF67
IF2
8
FF0
3
IF27
IF4
8
3
FG2-2
10K
10K
3
FG2-1
3
FG4-1
4K7
4K7
3
FG4-2
5FG0
3
0R
3
0R
5FE7
3
0R
10n
2FH
3
5FE9
T
S
-FE-VALID
T
S
-BR-VALID
T
S
-FE-
S
OP
T
S
-BR-
S
OP
T
S
-FE-CLOCK
T
S
-BR-CLOCK
T
S
-FE-DATA
T
S
-BR-DATA
+
3
V
3
-BRA
+
3
V
3
-BRA-FLT
IF-
S
CL-
SS
B
S
DA-
SS
B
IF-AGC
+2V5-BRA
+5V
+
3
V
3
+1V2-BRA-DR1
+
3
V
3
-BRA-FLT
RE
S
ET-
S
Y
S
TEMn
+1V2-BRA-VDDC
+
3
V
3
-BRA-FLT
+
3
V
3
-BRA-FLT
+2V5-BRA
+
3
V
3
-BRA
+2V5-BRA
IF+