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Block Diagrams, Test Point Overview, and Waveforms
57
Q523.1U LA
6.
Supply Lines Overview
S
UPPLY LINE
S
OVERVIEW
A
B01B
S
UPPLY
B01A
S
UPPLY
A
DI
S
PLAY
S
UPPLY
B02A
DC/DC
B02B
DC / DC
B02C
DC / DC
B0
3
A
CHANNEL DECODER
B0
3
B
MAIN TUNER
B04A
PNX
8
5xx:
S
TANDBY CONTROLLER
B04B
PNX
8
5xx: DEBUG
B04C
PNX
8
5xx: NVM / UART
S
WITCH
B04F
PNX
8
5xx: CONTROL
B04G
PNX
8
5xx:
S
DRAM
B04H
PNX
8
5xx: DIGITAL VIDEO IN
B04I
PNX
8
5xx: AUDIO
B04K
PNX
8
5xx: ANALOGUE AV
B04M
PNX
8
5xx: AUDIO
B04N
PNX
8
5xx: VIDEO
S
TREAM
S
B04O
PNX
8
5xx: DIGITAL VIDEO OUT / LVD
S
B04P
PNX
8
5xx: POWER
B04Q
PNX
8
5xx: FLA
S
H
B05B
FPGA 10
8
0P: POWER + CONTROL
B05C
FPGA 10
8
0P: I/O BANK
S
B05D
FPGA 10
8
0P: DRAM
B06A
PACIFIC
3
: LVD
S
B04L
PNX
8
5xx: AUDIO
B06B
PACIFIC
3
: DI
S
PLAY-INTERFACING
B06C
PACIFIC
3
B0
8
A
UART
B0
8
B
S
PDIF
B0
8
C
EXTERNAL
S
B0
8
D
HDMI
B0
8
F
HDMI
S
WITCH
B09A
ANALOGUE EXTERNAL
S
B10A
U
S
B 2.0
B10B
U
S
B 2.0
B11C
AUDIO: PROTECTION/MUTE CONTROL
J
LED
S
WITCH PANEL
B10C
LED PANEL CONNECTOR
B04D
PNX
8
5xx: MI
S
CELANEOU
S
B04E
PNX
8
5xx: CONTROL
B11A
AUDIO LEFT / RIGHT
AB06
FPGA DFI
AB05
FPGA: POWER + CONTROL
AB0
3
PNX
8
5
3
5: CONTROL
AB02
VIDEO-FLOW
AB01
DC/DC
AB07
DDR A
AB0
8
DDR B
AB09
DI
S
PLAY-INTERFACING
AB10
FPGA AMBILIGHT
1P11
1
1
6
6
7
7
2
2
3
3
4
4
5
5
8
8
S
TANDBY
BACKLIGHT-OUT
LAMP-ON-OUT
1P11
POWER-OK-DI
S
PLAY
BACKLIGHT-BOO
S
T
+5V-
S
TANDBY
9B06
+12V-DI
S
P
1B50
T
3
A
CONTROL
3
+AUDIO-POWER
+5V-
S
TANDBY
5B01
7
8
10
9
5
2
1
3
12
8
7B04
TCET1102
2
1
4
3
12
11
-AUDIO-POWER
6B07
6B0
8
2B4
8
2B51
+12V
S
7B06
6B05
1B
33
2.5AT
6B06
2B51
CONTROL
AUDIO-PROT
2B46
K
A
R
3
B72
6B15
3
B7
3
3
B29
7B50
B11C
2
1P02
1
7U01
D
ua
l
O
u
t-of-Ph
as
e
S
ynchrono
us
B
u
ck Controller
7U00
NCP5422
+12V
S
+12V
+12VF
7U06
+
3
V
3
15
1
2
7U0
3
7U0
8
+1V2
5U02
16
15
+12V
S
12V/1V2
COVERTER
12V/
3
V
3
COVERTER
7U16
5U00
5U0
3
+
3
V
3
F
7U2
8
1V
8
S
TAB.
7U27
+1V
8
+5V-POD
+5V-POD
1V2-
S
TANDBY
1V2-
S
TANDBY
+12V
S
+12V
S
+5V-POD
+12V
+12V
+5V-
S
TANDBY
+5V-
S
TANDBY
7U02-1
7U04-1
POD-MODE
7U02-2
7U04-2
ON-MODE
+5V-ON
7U19
+
3
V
3
-
S
TANDBY
+1V2-
S
TANDBY
3
U
8
6
7U20
7U17
VOLT.
REG.
7U1
8
VOLT.
REG.
(RE
S
ERVED)
+12VF
+12VF
+VTUN
3
UB
3
3
UB4
5U09
6U6
3
V
S
W
7U24
VP
VP
VN
VN
+
3
V
3
F
+
3
V
3
F
7U
8
C
+2V5
7U
8
B
VOLT.
REG.
7U61-1
S
TEP
DOWN
CONTR
7U64
L6910
+12VF
7U61-2
15
11
14
+12VF
5U6
8
+1V4
5U60
(RE
S
ERVED)
+12V
+12V
+
3
V
3
+
3
V
3
7T20
IN OUT
COM
+2V5-TUN
9T14
+
3
V
3
-AT
S
C
+5V-ON
+5V-ON
+1V2
+1V2
+5V-ON
+5V-ON
V2
V1
5T5
3
5T54
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+12V
+12V
+2V5
+2V5
+5V-ON
+5V-ON
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+5V
S
+5V
S
+
3
V
3
-PER
+
3
V
3
-PER
+1V
8
+1V
8
3
HJ
3
DDR2-VREF-DDR
3
HJ1
DDR2-VREF-CTRL
RREF-PNX
8
5
3
5
RREF-PNX
8
5
3
5
VP
VP
5HM0
AUDIO-VDD
VP
VN
5HM1
AUDIO-VEE
+
3
V
3
-PER
+
3
V
3
-PER
+5V
S
+5V
S
7HP0
IN OUT
COM
VDDA-AUDIO
5HP1
+
3
V
3
+
3
V
3
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+5V
S
+5V
S
+
3
V
3
-PER
+
3
V
3
-PER
+12V-DI
S
P
+12V-DI
S
P
VDDA-LVD
S
VDDA-LVD
S
5HY1
VDDA-LVD
S
VDDA-AUDIO
VDDA-AUDIO
5HY7
AUDIO-ADC
5HY4
VDDA-DAC
+1V2
+1V2
+1V
8
+1V
8
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+1V2-
S
TANDBY
+1V2-
S
TANDBY
+
3
V
3
+
3
V
3
+1V
8
-PNX
5HYA
+
3
V
3
-PER
7HK0
IN OUT
COM
RREF-PNX
8
5
3
5
5HK2
+
3
V
3
+
3
V
3
+
3
V
3
-NAND
5HA0
+
3
V
3
+
3
V
3
5FA
8
+Vin-FPGA
5FA6
+
3
V
3
-FPGA
7FA5
IN OUT
COM
+1V2-
S
TAB
7FA4
IN OUT
COM
+2V5-
S
TAB
5FA7
+2V5o
u
t-FPGA
+1V2-FPGA
5FB1
+1V2-PLL
5FA2
+2V5o
u
t-FPGA
+2V5o
u
t-FPGA
+
3
V
3
-FPGA
+
3
V
3
-FPGA
+1V2-FPGA
+1V2-FPGA
+Vin-FPGA
+Vin-FPGA
+1V2-PLL
+1V2-PLL
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
+
3
V
3
-
S
D1
5FK0
VDI
S
P
VDI
S
P
+12V-DI
S
P
+12V-DI
S
P
VDI
S
P
5G55
+
3
V
3
+
3
V
3
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+5V-ON
+5V-ON
7G54
+5V-
S
TANDBY
+5V-
S
TANDBY
+12V
+12V
+
8
V2-PA
S
3
GC4
+
3
V
3
+
3
V
3
5GE2
+
3
V
3
-P
3
7GE5
IN OUT
COM
+1V5
7GE
3
IN OUT
COM
+2V5-PF
5GE1
+2V5-PLL
+1V5-P
3
5GE
3
5GE0
+2V5-P
3
+1V5-TX
5GE5
+1V5-PLL
5GE4
+1V5-RX
5GE6
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+
3
V
3
+
3
V
3
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+
3
V
3
-UART
7J50
+12V
+12V
UART-
S
WITCH
7J51
AIN-5V
1B01
1
8
HDMI
CONNECTOR
BIN-5V
1B02
1
8
HDMI
CONNECTOR
CIN-5V
1B0
3
1
8
HDMI
CONNECTOR
+5V-CON
+5V-CON
5JA5
+5V-MUX
+
3
V
3
+
3
V
3
5JA4
+
3
V
3
-ANA
5JA
3
+
3
V
3
-DIG
+5V-CON
+5V
S
+5V
S
+12V
+12V
+5V
S
+5V
S
+
3
V
3
+
3
V
3
+5V-ON
+5V-ON
+5V
S
+5V
S
+AUDIO-POWER
+AUDIO-POWER
VPP
-AUDIO-POWER
-AUDIO-POWER
ON-MODE
7D5
8
3
D04
VP
7D55
ON-MODE
3
D04
VP
7D55
3
D
3
9
VN
7D61
VNN
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
VP
VP
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
VN
VN
VPP
VPP
VNN
VNN
+5V-
S
TANDBY
+5V-
S
TANDBY
1M20
5
B10C
TO 1M20
SS
B
1M20
5
TO 1M20
IR/LED
J
3
JC
8
3
JC7
3
JH
3
B11
a
B11
a
B11
a
B11
a
B02
b
B02
b
B01
a
B01
a
B02
b
B02
b
B02
a
B02
b
B02
a
B02
a
B0
8
d
B02
b
B11c
B02
b
,B04i,
B11c
B11c
B02
b
,B04i,
B11c
B0
8
F
B11
a
B11
a
B01
a
B02
b
B02
a
,
b
,
B02
b
,c,
B04
a
,B06
b
,
B0
8
c,B09
a
B02
b
,c,B
3a
,
b
,
B04
a
,e,l,m,p,
q
B05
b
,c,d,B06
b
,c,
B0
8b
,f,B10
a
+5V
S
3
U94
B04c,d,l,m
B09
a
,B10c
B0
3a
,B04
a
,
b
,
B06
b
,B10
b
B02
a
,B04p
B04
a
,
b
,c,d,e,m,p,
B06
b
,B0
8a
,c,B11
a
,c
B05c
B05c
B05c
B05c
B05c
B06
a
B02
a
B02
a
B05
b
B05
b
B05
b
B05
b
B02
a
B05
b
B02
a
B06
b
B01
b
B02
b
B02
a
B02
b
B02
b
B02
a
B02
a
B02
a
B02
b
B02
a
B02B
B02
a
B04p
B02
a
B04p
B11
a
B11
a
B04p
B02
b
B02
b
B02
a
B02
b
B04p
B01
b
B04p
B02
a
B02
a
B02
b
B02
b
B02
a
B04l
B04o
B04e,f,k,n
B04h
B04p
B02
b
B02
b
B02
b
B02
b
B02
a
B02c
B02
a
B02
b
B02
b
B02
a
B02
b
B02
a
B02
a
B02
a
B02
a
B02
a
B02
a
B02
a
B11
a
B11
a
B01
a
B01
a
B04
a
B01B,B02
b
,
B06
b
B01
a
B06
b
,B04o
B02
b
,c
B0
3a
,B04e
1M09
1
2
3
4
TO
AMBI-LIGHT
B02
b
B02
a
B06B
B04A
B06B
B04D
N.C.
S
EE AL
S
O BLOCK DIAGRAM
S
UPPLY
S
EE AL
S
O BLOCK
DIAGRAM
S
UPPLY
S
TANDBY
x
7U14
POD-MODE
9U
8
A
+
3
V
3
+
3
V
3
B02
a
H_16770_075.ep
s
060907
3
U01
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+5V
S
+5V
S
+
3
V
3
-PER
+
3
V
3
-PER
+
3
V
3
-
S
TANDBY
+
3
V
3
-
S
TANDBY
+1V2
+1V2
+
3
V
3
+
3
V
3
RE
S
B02
b
B02
b
B02
b
B02
a
B04p
B02
a
1
1F50
+12V-
SS
B
1F51
1
TO 1G50
SS
B
B06A
+
3
V
3
+
3
V
3
+1V2
+1V2
+1V2-PLL
+1V2-FPGA
5F54
5F55
5F5
3
+2V5
+2V5
5F24
+2V5o
u
t-FPGA
5F2
3
+Vin-FPGA
5F25
+2V5in-FPGA
+
3
V
3
+
3
V
3
AB06
AB06
AB06
AB06
AB06
+VDI
S
P
TO
DI
S
PLAY
AB09
AB01
AB01
AB01
+VDI
S
P
+12V
S
1M90
1
+12V
1U01
3
.0AT
5U05
+12V-DC
1U02
3
.0AT
5U06
5U07
+
3
V
3
7U0
8
IN OUT
COM
7U09
IN OUT
COM
7U0
3
-1
D
ua
l
O
u
t-of-Ph
as
e
S
ynchrono
us
B
u
ck Controller
7U00
NCP5422
7U0
3
-2
+1V2
14
15
16
7U01-1
7U01-2
+2V5
5U01
1
2
12V/1V2
COVERTER
12V/
3
V
3
COVERTER
3
U01
5U02
AB0
3
,AB05,
AB06,AB09,
AB10
AB05,AB07,
AB0
8
,AB10
AB05,AB10
TO 1M90
S
UPPLY
AB01
+2V5o
u
t-FPGA
+2V5o
u
t-FPGA
2V5-DDR2
2V5-DDR2
+1V2-FPGA
+1V2-FPGA
+Vin-FPGA
+Vin-FPGA
+1V2-PLL
+1V2-PLL
2V5-DDR1
2V5-DDR1
VREF-FPGA1
VREF-FPGA1
+2V5in-FPGA
+2V5in-FPGA
VREF-FPGA2
VREF-FPGA2
+
3
V
3
+
3
V
3
AB0
8
AB05
AB05
AB05
AB05
AB06
AB05
AB07
AB0
8
AB01
VREF-FPGA1
+2V5
+2V5
5F27
VREF-DDR1
5F2
8
+2V5-DDR1
3
F4B
3
F4D
VREF-FPGA2
+2V5
+2V5
5V01
VREF-DDR2
5V02
+2V5-DDR2
3
CD6
3
CD
8
+12V
+12V
+VDI
S
P
5F0K
7F07
5F0L
5F0M
3
F4
8
+5V
+
3
V
3
+
3
V
3
AB02
AB06
AB06
AB06
AB06
AB01
AB01
AB01
+
3
V
3
+
3
V
3
+
3
V
3
M
AB01
5F
3
1
+2V5
+2V5
+2V5M
AB01
5F
3
4
+1V2
+1V2
+1V2M
AB01
5F
33
+1V2-PF
9F52
AB01
1M90
1
2
3
4
1M90
DFI PANEL
5
6
1G50
41
TO 1F50
DIF
AB02
5U04
+12V
+12V
+12V
+12V
+12V
GND
GND
GND
GND
GND
Dim-control
Power-Good
Light_on_off
GND
Boo
s
t
+12V
S
t
a
nd
b
y
+5v2