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Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 137
Q523.1U LA
9.
Figure 9-1 Architecture of TV520 platform
Sets with a resolution of 1366
×
768p @ 60 Hz use the
PNX85xx SoC and the T6TF4HFG PACIFIC 3 for video
processing. Sets with a resolution of 1920
×
1080p @ 60 Hz
use the EP2C8F Cyclone FPGA in addition which also drives
the AmbiLight units. To achieve 1920
×
1080p @ 120 Hz
however, an additional panel is used for Dynamic Frame
Insertion (DFI).
Refer to section “Video Processing” in this chapter for more
details.
FLA
S
H
8
Matrix
1920x10
8
0p@60Hz
1920x10
8
0p@120Hz
Matrix
1920x10
8
0p@60Hz
1920x10
8
0p@120Hz
TDA10060
V
S
B-QAM
EP2C
8
F
T6TF4HF6
Matrix converter
+
Cyclone II FPGA
Ambient li
g
ht
Pacific
3
MA
S
TER IF
UV17
3
6
Tuner/
S
aw
DDR-II
DDR-II
Audio Amp.
PNX
8
5xx
MIP
S3
2@250MHz
TV Control,
Audio/video decodin
g
Analo
g
and di
g
ital
MUX
max.
3
HDMI
DDR
DDR
EPLD DFI@10
8
0p
DDR
DDR
QUAD LVD
S
1920x10
8
0P@120Hz
DUAL LVD
S
1920x10
8
0P@60Hz
DUAL LVD
S
1920x10
8
0P@60Hz
Optional: Dynamic Frame In
s
ertion (DFI)
Conver
s
ion 60Hz to 120Hz @10
8
0p
Platform Picture
quality,
S
calin
g
Picture
Quality
feature
s
H_16770_102.ep
s
070907