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56
Q523.1U LA
6.
Block Diagrams, Test Point Overview, and Waveforms
I2C IC Overview
I²C
PNX
8
5xx: CONTROL
B04E
PACIFIC
3
: DI
S
PLAY-INTERFACE
B06B
PACIFIC
3
: LVD
S
B06A
CHANNEL DECODER
B0
3
A
MAIN TUNER
B0
3
B
FPGA 10
8
0P: I/O BANK
S
B05C
PACIFIC
3
B06C
MAIN TUNER
B0
3
B
PNX
8
5xx:
S
TANDBY CONTROLLER
B04A
PNX
8
5xx: NVM / UART
S
WITCH
B04C
PNX
8
5xx: DIGITAL VIDEO IN
B04H
PACIFIC
3
: DI
S
PLAY-INTERFACING
B06B
S
UPPLY
B01B
EXTERNAL
S
B0
8
C
UART
B0
8
A
PNX
8
5xx: DIGITAL VIDEO OUT / LVD
S
B04O
HDMI
S
WITCH
B0
8
F
HDMI
B0
8
D
VIDEO-FLOW
AB02
DI
S
PLAY
INTERFACING
AB09
FPGA DFI
AB06
DI
S
PLAY INTERFACING
AB09
FPGA AMBILIGHT
AB10
1
8
1M59
3
1
1HP0
3
1
2
S
DA-
SS
B
S
CL-
SS
B
AJ27
7H00
PNX
8
5
3
7E
PNX
8
5xx
AJ2
8
70
69
7T1
8
TDA10060HL
CHANNEL
DECODER
ERR
3
7
+
3
V
3
-PER
3
HPM
3
HPK
3
T
38
3
T
3
7
3
HPJ
3
HPH
19
1
1
8
2
3
x HDMI
CONNECTOR
7JA0
M24C02
EEPROM
5
6
3
JA
8
3
JA
7
5
6
3
JC0
3
JB6
7JA1
M24C02
EEPROM
8
5
8
6
9
3
94
ARX-DDC-
S
DA
ARX-DDC-
S
CL
BRX-DDC-
S
DA
BRX-DDC-
S
CL
PARX-DDC-
S
DA
PARX-DDC-
S
CL
PBRX-DDC-
S
DA
PBRX-DDC-
S
CL
ERR
05
I2C
3
-
S
DA
I2C
3
-
S
CL
I2C2-
S
DA
I2C2-
S
CL
I2C1
S
DA
I2C1-
S
CL
ERR
5
3
1
2
3
JA0
3
JC5
3
JB0
S
DA
3
S
CL
3
S
DA-
SS
B-MUX1
S
CL-
SS
B-MUX1
+
3
V
3
-
S
TANDBY
3
HPY
3
HPX
3
HP
S
3
HPR
4
5
7HP5
PCA9540BDP
9G5
3
9G54
S
DA-I2C4-DI
S
P
S
CL-I2C4-DI
S
P
1G50
1
2
3
G52
3
G5
3
LVD
S
COONECTOR
TO DI
S
PLAY
OR
S
DA-
SS
B-MUX2
S
CL-
SS
B-MUX2
+
3
V
3
-
S
TANDBY
3
HPC
3
HPZ
3
HPU
3
HPW
7
8
3
HPA
3
HPB
3
HPT
3
HPQ
AK2
8
AK29
S
DA2
S
CL2
S
DA-UP-MIP
S
S
CL-UP-MIP
S
AH27
AK27
S
DA1
S
CL1
S
DA-
S
LAVE
S
CL-
S
LAVE
3
HPE
3
HPD
9HP6
9HP5
9HP
8
9HP7
3
HPG
3
HPF
S
DA-2
S
CL-2
S
DA-
SS
B1
S
CL-
SS
B1
9T16
9T15
2
3
24
7T57
TDA9
8
97HL
IF
PROCE
SS
ING
ERR
26
3
T57
3
T56
C1
C2
7F90-2
EP2C
8
F256C7N
FPGA 10
8
0P
(EPLD)
ERR
2
8
3
F95
3
F9
8
19
8
200
7GE2-2
T6TF4HFG
PACIFIC
3
ERR
46
3
GG2
3
GG
3
9T
8
5
9T
8
6
S
DA-MUX2-BUF
S
CL-MUX2-BUF
7
6
1T04
TD17
3
6F
MAIN
TUNER
ERR
3
4
3
T77
3
T5
3
9T51
9T52
AH
3
AG4
3
H41
3
H
38
B04A
+
3
V
3
-
S
TANDBY
3
H0
3
3
H02
5
6
7HC
3
M24C64
EEPROM
(MAIN NVM)
RE
S
ET-NVM_WP-NANDFLA
S
H
DDC-
S
DA
DDC-
S
CL
E10
C9
DDC-
S
DA
DDC-
S
CL
DDC-
S
DA
DDC-
S
CL
B04H
3
F9
3
3
F94
E1
E2
S
DA-AMBI-
3
V
3
S
CL-AMBI-
3
V
3
7G61-2
7G61-1
3
B59
3
B5
8
+5V-ON
3
GA
3
3
GA0
+
3
V
3
S
DA-AMBI
S
CL-AMBI
5B10
5B12
RXD
TXD
AB1
AC5
3
H59
3
H61
RXD-UP
TXD-UP
RXD
TXD
E27
D2
8
RXD-MIP
S
TXD-MIP
S
7HC0
74HC4066PW
9
2
RXD
TXD
10
3
3
HC
3
3
HC6
10
9
R2-OUT
T2-IN
8
7
RXD-
S
ERV
TXD-
S
ERV
3
JE5
3
JE4
T2-OUT
R2-IN
7JE2
S
T
3
2
3
2C
1M15
3
2
UART
S
ERVICE
CONNECTOR
3
J11
3
J12
B0_UART
B1_UART
AF15
AK16
DV-B0_UART2-RX
DV-B1_UART2-TX
B04O
9HWH
9HWG
11
12
R1-OUT
T1-IN
50
49
7J27
AD
8
191A
S
TZ
HDMI
S
WITCH
ERR
2
3
3
J29
3
J09
90
8
9
S
DA-
SS
B
S
CL-
SS
B
9
8
99
CRX-DDC-
S
DA
CRX-DDC-
S
CL
PCRX-DDC-
S
DA
PCRX-DDC-
S
CL
3
JG7
3
JG6
5
6
3
JG5
3
JH6
7J29
M24C02
EEPROM
1B01
16
15
1B02
16
15
1B0
3
16
15
AIN-5V
3
JA
6
3
JA
5
BIN-5V
3
JB5
3
JB4
CIN-5V
3
JG
3
3
JG2
TO AMBI-LIGHT
NODULE
7H02
M25P05
512
FLA
S
H
U4
UART-
S
WITCH
HDMI
S
TANDBY
CONTROL
4
11
1HE2
1
2
3
UART2
FOR
FACTORY
U
S
E ONLY
T1-OUT
R1-IN
RXD2
TXD2
1
3
14
R
S
2
3
2
INTERFACE
H_16770_074.ep
s
070907
VID_OUT
TTL
ERR
0
3
ERR
11
ERR
12
ERR
24
P0.1
P0.7
V
3
7HC4
8
3
JE
3
3
JE2
9J06
9J07
2 CHANNEL
I2C
MULTIPLEXER
1M59
3
1
7F09-2
7F09-1
3
F45
3
B44
+5V
3
F
3
7
3
F
38
+
3
V
3
S
DA-AMBI-
3
V
3
S
CL-AMBI-
3
V
3
P2
P1
7F1
8
EP2C
3
5F4
8
4C7N
CYCLONE II
(FPGA)
ERR
65
3
FA
0
3
F49
3
F19
3
F20
1F50
41
40
S
DA-I2C4-
SS
B
S
CL-I2C4-
SS
B
S
DA-I2C4
S
CL-I2C4
B4
A5
3
F6J
3
F9E
Only for 120Hz
Dyn
a
mic Fr
a
me In
s
ertion
Only for 120Hz
Dyn
a
mic Fr
a
me In
s
ertion
TO AMBI-LIGHT
MODULE
P11
R11
7F65
XC
3S
250E
4FTG256C(XILI)R
S
PARTAN
FPGA
3
F9G
3
FPH
Only for 120Hz
Dyn
a
mic Fr
a
me In
s
ertion
With AMBI-LIGHT
Only for 120Hz
Dyn
a
mic Fr
a
me In
s
ertion
With AMBI-LIGHT
3
JA1
UART
LEVEL ADAPTER