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Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 150
Q523.1U LA
9.
9.7.2
Full-HD sets @ 60 / 120 Hz
In full-HD sets @ 60 Hz, the output signal coming from the
PNX85xx is fed to the PACIFIC3 via a single LVDS connection.
In full-HD sets @ 120 Hz, the YUV output signal coming from
the PNX85xx is fed to the CYCLONE II FPGA and then
connected to the PACIFIC 3 via a double LVDS connector. The
CYCLONE II FPGA drives the AmbiLight units via I
2
C. The
PACIFIC 3 also generates the pulse-width modulated signal
needed for the “Dimming Backlight” feature, which ensures
additional motion sharpness. As some displays require an
analog signal to switch the LCD, a multiplexer is added to
transform the pulse-width modulated signal. An additional
signal, coming from the PNX85x, makes the selection between
analog and pulse-width modulation, depending on which
display is used. Scanning Backlight displays require an analog
signal, and all other displays a pulse-width modulated. The
signal for “Scanning Backlight” is an I
2
C signal coming from the
PNX85xx.
Refer to figure “Block diagram display control Full-HD sets 60 /
120 Hz”.
Figure 9-16 Block diagram display control Full-HD sets 60 / 120 Hz
H_16770_128.eps
130707
TV520/30 – fHD 50/60/100/120Hz
LV
D
S
41p -
F
I-
R
4
1S
-H
F
1M
5
9
1D
42
Pacific 3
SPI -flash
M25P05-AVMN6P
9322 206 45668
PNX85xx
M2
1S
01
I2C-Scanning (no dimming)
PWM (Analog )
Dimming
MUX
+
Level
shift
LV
D
S
F
I-
W
E
31
P
-H
F
Debugging only !!
Select -AnaPWM Dimming
Converter
+
MUX
PWM
Dimming
Analog (PWM)
Dimming
MIPS
StdBy
PWM Boost
Converter
Analog Boost
YUV
10b
LVDS
10
60Hz
120Hz
b
LVDS
10b
JUM
PERS
MOP2K7-
LVDS
Cyclone II
Flash
I2C-Ambi
LVDS
fHD
fHD DF
with DFI
AmbiLight
Scanning
Backlight
Display
Supply