Chapter 2: Introduction
40
Processor Interface
There is a parallel connection to the AMCC 440GX CPU. This connection is used for the
configuration and control of the TDM switch.
For information on how to use the registers in the H.110 TDM switch, refer to the
Zarlink
Semiconductor MT9866 WAN Access Switch Datasheet
.
The H.110 TDM switch has several interrupt outputs that connect directly to the 440GX. They
are mapped as shown in
Table 2-7, “TDM Interrupt Mapping,”
below.
The FAIL_PRI_INT and FAIL_SEC_INT interrupts indicate that the system timing reference
inputs have either stopped or are out of specification according to the internal detection logic.
The FAILA_INT and FAILB_INT indicate that there has been a failure in the A or B side clocks
on the J4 CT bus.
TDM Multiplexer Registers
The TDM multiplexer CPLD connects local TDM input and output streams on the MT90866
switch to various TDM connections on the two PTMC slots. The connection from the switch to
the CPLD is unidirectional and fixed. The CPLD outputs to the PTMC slots are unidirectional
but can be programmed as inputs or outputs individually. There is a register file inside the
CPLD that determines what the direction of the PTMC connection is and to which port on the
MT90866 that the PTMC line is mapped.
TDM Multiplexer Reverse Endian
The TDM multiplexer PLD has the capability of reversing the endian of the TDM bit stream. The
reverse endian function may be performed on up to 896 DS0s (seven streams, STI/O 6 – 12) of
the dedicated lines from the Zarlink to TDM multiplexer interface. The minimum connection
allocation of the reverse endian function is 128 DS0s (1 stream). Once a bit stream has been
allocated to implement the reverse endian function it can no longer be used as an available
PTMC connection stream. The reverse endian function is accomplished by writing a control
command in the respective TDM switch input (6 – 12) mux register that has been chosen to
perform the reverse endian function. Implementing the reverse endian function reverses the
individual bit order, however the TDM mux PLD inserts one timeslot delay per DS0 channel.
Table 2-7:
TDM Interrupt Mapping
MT90866 Interrupt
440GX Interrupt Connection
FAIL_PRI_INT
IRQ06
FAIL_SEC_INT
IRQ07
FAILA_INT
IRQ08
FAILB_INT
IRQ09
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