CPC324 Functional Blocks
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The H.110 switch interfaces the T1/E1/J1 LIU and framers with the AMCC 440GX's main
memory through one of three Mindspeed multichannel communication controllers. The switch
can also route the TDM data to or from the two on-board PTMC sites. The TDM switch is fully
compliant with the ECTF H.100/H.110 specification and has no restrictions to the possible
types of switching connections that can be made. Each local timeslot can be assigned to any of
the possible 4096 H.110 external timeslots or reassigned to any other local timeslot.
The hot-swap CompactPCI interface provides PCI bus initiator/target mode capability of 32/64-
bit data accesses at 33/64 MHz bus rates. The hot-swap controller supports high availability,
which implements a high degree of control and allows orderly insertion and extraction of the
CPC324.
The on-board Ethernet switch allows the AMCC 440GX CPU to be interconnected with the dual
on-board PTMC sites and the external CompactPCI 2.16 backplane connections. An option on
the RTM allows the 2.16 connections to be routed out the RTM's face plate to allow connection
to external connections. The CPC324 also supports an Ethernet management port on its front
panel.
AMCC 440GX
The AMCC 440GX is a Power PC processor. It is used for Gigabit Ethernet, I2O Messaging
Units, and TCP/IP acceleration hardware.
AMCC 440GX Local PCI Bus
The AMCC 440GX PCI interface allows connection of local on-board PCI devices to the
PowerPC processor and local memory. This interface is designed to version 2.3 of the PCI
specification and supports 32 bit, 33 MHz transfers. The AMCC 440GX features three on-chip
buses:
•
Processor Local Bus (PLB)
•
On-Chip Peripheral Bus (OPB)
•
Device Control Register Bus (DCR)
The high performance, high bandwidth cores such as the PowerPC 440 processor core, the
DDR SDRAM memory controller, and the PCI bridge connect to the PLB. The OPB hosts lower
data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing
status and control information between the processor core and the other on-chip cores.
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