Introduction
1230B0026701
1-10
Checkpoint Description
FA
Check the validity of the recovery file configuration to the current configuration of
the flash part.
FB
Make flash write enabled through chipset and OEM specific method. Detect proper
flash part. Verify that the found flash part size equals the recovery file size.
F4
The recovery file size does not equal the found flash part size.
FC
Erase the flash part.
FD
Program the flash part.
FF
The flash has been updated successfully. Make flash write disabled. Disable ATAPI
hardware. Restore CPUID value back into register. Give control to F000 ROM at
F000:FFF0h.
Table 1-7 POST Code Information
Checkpoint Description
03
Disable NMI, Parity, video for EGA and DMA controllers. Initialize BIOS, POST,
and Runtime data area. Also initialize BIOS modules on POST entry and GPNV area.
Initialize CMOS as mentioned in the Kernel Variable "wCMOSFlags".
04
Check CMOS diagnostic byte to determine if battery power is OK and CMOS
checksum is OK. Verify CMOS checksum manually by reading storage area. If the
CMOS checksum is bad, update CMOS with power-on default values and clear
passwords. Initialize status register A.
Initialize data variables that are based on CMOS setup questions. Initialize both the
8259 compatible PICs in the system
05
Initialize the interrupt controlling hardware (generally PIC) and interrupt vector table.
06
Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the
POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt.
Trap INT1Ch vector to "POSTINT1ChHandlerBlock".
08
Initialize the CPU. The BAT test is being done on KBC. Program the keyboard
controller command byte is being done after Auto detection of KB/MS using AMI
KB-5.
C0
Early CPU Init Start -- Disable Cache - Init Local APIC
C1
Set up boot strap processor information
C2
Set up boot strap processor for POST
C5
Enumerate and set up application processors
C6
Re-enable cache for boot strap processor
