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PCI Interface Device Summary

S5933QE

B4: SERR# and INTA# Driven during FLT# Assertion 

Description: Driving the FLT# signal low tri-states all S5933 pins with the exception of SDA, SCL, SERR# and INTA#. The SDA

and SCL are unaffected by the FLT# signal. The SERR# and INTA# are driven low as long as FLT# is low.

Workaround: See the

 CompactPCI

 Hot Swap design note for a solution should the FLT# signal be required in a design.

Status: : No factory plan to re-spin.

B5: Bus Master Data Loss Following a Master Abort or Special Cycle

Description: The S5933 PCI Bus Master engine will read or write one DWORD using the wrong address when bus mastering

resumes if, after S5933 bus ownership is lost, a special cycle or master abort occurs before the bus mastering resumes
and is completed. This applies only to systems using  chip sets which drive AD[31::11] to a logic one during master aborts
and special cycles.

Workaround: A) Move the S5933 to a slot which does not assert IDSEL from an AD[31::11] logic one condition during special

cycles or  Master aborts.

       B) Block the IDSEL signal to the S5933 from Add-On side before bus mastering.
       C) Decode the CB/E signal when FRAME# is asserted and block IDSEL if not a configuration read or write.

Status: : No factory plan to re-spin.

NOTE:

   The 1997 S5933 data book incorporates many updates and clarifications over the Spring 1996 data book. The 1997 and

1998 data books reflect the S5933QB, QC and QE silicon functions and operation with the exception of each device’s
respective device summary documents.

B6: REQ# Fall Time May Cause Arbiter/System Lock-Up

Description: The S5933’s PCI Bus REQ# output signal may not have enough drive power to provide a sufficient REQ# fall time

for some arbiters. A slow fall time when used in systems containing a Winbond arbiter or Intel 440BX chip set may cause
a system lock-up.

Workaround: Connect an external buffer between the S5933’s REQ# output pin and the card’s PCI Bus edge connector. The

propigation delay of the buffer selected should not exceed 4 ns. An example low cost small SOT23 device from Fairchild
Semiconductor can be seen at http://www.fairchildsemi.com/pf/NC/NC7SZ126.html.

Status: : No factory plan to re-spin.

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