User Manual For Cyclone LC Programmers
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After the basic hardware setup, target power and voltage settings are also set in the creation of a
SAP (stand-alone programming) image. At a minimum the SAP image contains all the commands
to Erase, Program, and Verify a programming image. More sophisticated power selections in the
SAP image can control the relays, target voltage, delays, and power down after SAP operations,
as shown in the selection dialog.
Figure 4-4: Target Power & Voltage Settings
Target voltages (with appropriate jumper settings) in the range of 1.6 to 5.5 volts may be provided.
There is also the option to select the internal Cyclone relays to power cycle the Cyclone during
programming, and set the length of delays during power up and down. This is extremely useful to
make sure the power is off when hooking up the target. Power cycling is especially important for
architectures that require it to enter debug mode. The SAP image settings may even be used to
turn off the target power once programming is completed, to ensure that the microcontroller is left
in a halted state and not running.
4.2
Cyclone Setup
Below is a tutorial that demonstrates how to set up the
Cyclone LC
in each of the 5 power
configurations. A very common configuration is the independently powered target. In this power
scenario, the Cyclone will detect and use the power on the target for the appropriate debug
communication voltages.
4.2.1
Independently Powered Target
In the simplest and most common scenario, no jumpers are set, so the target is powered
independently from the Cyclone. No power is passed through the debug header, just the standard
debug signals. The Cyclone automatically detects the target power and sets the debug signals to
match.
Figure 4-5: Independently Powered Target
4.2.2
Power provided by the Cyclone to the debug cable
It is also possible for the Cyclone to generate power through an internal regulator in the range of
1.6 to 5.5 Volts. In the jumper configuration below, the Cyclone generates the power through a
voltage regulator, and passes it through the power relays and out through the debug ribbon cable,
which is set up during the SAP image creation. There is only one connection to the target
processor which will handle both the communication and the power. In this scenario, external
power must not be connected to the Power In jack since it is already being provided.
