Panasonic Viera TC-P54Z1, Technical Manual

Page: 29 / 93

Slide #29
Display Unit - Digital Signal Processing (Wired)
Circuit Explanation
When the Tuner is wired to the Display, TMDS Data Clock, DDC IIC, and HDMI CEC from the Tuner
are connected to the Display Unit via the HDMI cable.
The TMDS data and the DDC-IIC are provided to an Equalizer circuit in the GH board to equalize the
signals encoded in the transition-minimized differential signaling (TMDS) format.
The Equalizer is used to compensate for signal decay and degradation due to cables and connectors
via high-precision impedance matching.
It extends TMDS cable reach to the Display Unit allowing use of long cables.
In the DA board, the TMDS data and the DDC-IIC are connected to IC25510 (HDMI Receiver/Sound
Processor) where the signal is processed.
The video and the audio are separated inside IC25510. The PWM audio is outputted to the audio
amplifiers IC22301 and IC22302.
The processed 36bit Digital RGB Video Signal is output to the global core 6 (GC6) IC25100.
The Video signal is then mixed with the OSD data from the PEAKS AVC IC28001.
The signal is then converted to LVDS and is outputted to IC29300 (Plasma AI, Sub Field Processor,
and HV Sync Control).
IC29300 outputs video data pulses to drive the data drive boards (C boards).
IC29500 outputs the sustain and scan control pulses to drive the scan and the sustain circuits in the
SC and SS boards respectively.