4
6-4
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
REC VIDEO SIGNAL
PB VIDEO SIGNAL
REC AUDIO SIGNAL
PB AUDIO SIGNAL
MAIN C.B.A.
46
44
39
37
40
8
11
RF AMP
RF GAIN
CONTROL
FROM/TO
SYSTEM CONTROL
BLOCK DIAGRAM
18
8
7
17
19
1
21
TP3207
PB CLOCK
67
68
69
70
EQ SERIAL CLOCK
EQ SERIAL CLOCK
EQ SERIAL DATA
EQ SERIAL DATA
EQ STROBE PULSE
EQ STROBE PULSE
DATA (4 BIT)
ADDRES/DATA
(0) - (15)
ADDRES/DATA
(0) - (15)
BUS CLOCK
MEMORY READ
MEMORY WRITE
ADDRESS STROBE
CLOCK 2 (18 MHz)
TO/FROM
AUDIO
BLOCK DIAGRAM
AUDIO DATA 0
DSF DATA
(8 BIT)
AUDIO DATA 1
AUDIO BIT CLOCK
AUDIO MASTER CLOCK
AUDIO L/R CLOCK
FROM/TO VIDEO
SIGNAL PROCESS I
BLOCK DIAGRAM
IC3201 (SHUFFLING/FORMATTING)
IC3203(EQUALIZER)
IC3204 (RF AGC)
IC3202 (IEEE1394 INTERFACE)
FP5
12
FP5
1
B3
30
FP5
15
FP5
2
FP5
3
FP5
4
FP5
6
FP5
7
FP5
8
FP5
13
FP5
11
FP5
9
FP501
5
FP501
3
FP501
4
FP501
2
TO/FROM
SYSTEM CONTROL
BLOCK DIAGRAM
30
10
JACK C.B.A.
10
30
29
34
33
36
31
32
35
GCA
IEEE1394
INTERFACE
MICROCONTROLLER
INTERFACE
A/D
AGC
DET
16 17 18 19 20 21
AMP
LPF
LOGIC
IC5001 (HEAD AMP)
HEAD AMP C.B.A.
CH 1
HEAD
CH 2
HEAD
ENVELOPE
TO INTERFACE BOARD
(FOR EVR ADJUSTMENT)
JK3703
DV JACK
(FROM SAFETY TAB SW)
S-TAB ON (L)
3
7
9
12
15
21
SHUFFLING
MEMORY
SHUFFLING
CONTROL
DCT
VLC
DV-BUS
INTERFACE
A/D, D/A
INTERFACE
NOISE
CANCELLER
SYNCHRONISE
CONTROL
89
85
88
87
86
TO/FROM VIDEO
SIGNAL PROCESS I
BLOCK DIAGRAM
FS SELECT 0
FS SELECT 1
FS CLOCK
CLOCK 1 (18 MHz)
CLOCK 2 (18 MHz)
FS SELECT 0
FS SELECT 1
FS CLOCK
CLOCK 1 (18 MHz)
CLOCK 2 (18 MHz)
176
118
120
28
31
126
129
47
2
12
125
REC CONTROL
69
HEAD SW PULSE 2
68
HEAD SW PULSE 1
HEAD SW
PULSE 1
66
PB (H)
PB (H)
63
REC ON/OFF CONTROL
REC
ON/OFF
CONTROL
44
38
78
79
ATF CONTROL
AFT
CONTROL
EQ
HOLD
CLOCK
(18MHz)
124
REF CLOCK
REF
CLOCK
127
REC CLOCK
XO
XI
REC
CLOCK
45
REC-C CONTROL
50
49
42
6
AGC
AMP
7
39
43
45
ECC MEMORY
CONTROL
/DE-SHUFFLING
ECC MEMORY
ENCODER
ERROR
CORRECTION
DECODER
113
110
108
105
102
99
97
94
24
23
22
116
117
118
124
CLOCK(24.576MHz) 81
BUS CLOCK
DATA CMPLT
DATA CMPLT
119
102
234
194
82
83
240
237
223
226
TP3206
TP3203
TP5002
TP5003
TP5001
TP5005
MEMORY READ
75 CLOCK(24.576MHz)
MEMORY WRITE
ADDRESS STROBE
MEMORY READ
MEMORY WRITE
ADDRESS STROBE
FP6
7
FP6
8
FP6
5
FP6
6
FP3701
9
FP3701
8
FP3701
11
FP3701
10
1
5
2
3
4
TPB(-)
TPB(+)
TPA(-)
TPA(+)
GND
DE-
SHUFFLING
SHUFFLING
MEMORY
VITERBI
EQ
A/D
ATF AMP
24.576MHz
OSC
X3201
115
Summary of Contents for PV-DAC10
Page 38: ...2 24 Dumper Unit Fig DM6 6 Dumper Unit S 4 ...
Page 52: ...2 38 Loading Motor Unit Fig DM20 26 Loading Motor Unit S 11 chassis holes Bosses ...
Page 58: ...2 44 MIC Switch Fig DM26 34 MIC Switch S 15 Bosses chassis holes ...
Page 60: ...2 46 T4 Drive Arm Fig DM28 36 T4 Drive Arm ...
Page 195: ...Printed in Japan ...