Chapter 20
Appendix
Instruction set
XX - 9
Mnemonic
*1 *3
*2 *3
*1 *3
*2 *3
*1 *3
*2 *3
*1 *3
*2 *3
*6
*7 *8
*4
*5
*6
*7 *8
1
1110
1110
0001
0001
0101
0101
1111
1111
0001
1001
1101
0001
0001
0001
1001
1101
EXT.
0011
0011
0011
0011
0011
0011
0011
0011
0010
0011
0011
0010
0011
0011
2
0bp.
1bp.
0bp.
1bp.
0bp.
1bp.
0bp.
1bp.
00A0
0aaH
1010
00A1
000H
001H
1aaH
1011
3
<abs
<abs
<abs
<abs
<io8
<io8
<abs
<abs
<abs
000B
<d12
<d16
<abs
000B
4
16..
16..
8..>
8..>
...>
...>
16..
16..
18.b
bbbH
....
....
18.b
bbbH
5
....
....
<d7.
<d11
<d7.
<d11
....
....
p15~
<abs
...>
....
p15~
<abs
6
....>
...>
..H
....
...H
....
...>
...>
0..>
20.b
...>
0..>
20.b
7
<d7.
<d11
...H
...H
<d7.
<d11
p15~
p15~
8
...H
....
...H
....
0..>
0..>
9
...H
...H
10
11
9
10
7
8
7
8
9
10
3
7
9
3
5
6
7
9
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
4+d/6+d+i
3+i
3+i
4+i
max(2+i,4+2d)
max(2+i,4+2d)
max(2+i,4+2d)
max(2+i,4+2d)
max(3+i,5+2d)
if(mem8(abs16)bp=0),
PC+9+d7(label)+H
→
PC
if(mem8(abs16)bp=1), PC+9
→
PC
if(mem8(abs16)bp=0),
PC+10+d11(label)+H
→
PC
if(mem8(abs16)bp=1), PC+10
→
PC
if(mem8(abs8)bp=1),
PC+7+d7(label)+H
→
PC
if(mem8(abs8)bp=0), PC+7
→
PC
if(mem8(abs8)bp=1),
PC+8+d11(label)+H
→
PC
if(mem8(abs8)bp=0), PC+8
→
PC
if(mem8(IOTOP+io8)bp=1),
PC+7+d7(label)+H
→
PC
if(mem8(IOTOP+io8)bp=0), PC+7
→
PC
if(mem8(IOTOP+io8)bp=1),
PC+8+d11(label)+H
→
PC
if(mem8(IOTOP+io8)bp=0), PC+8
→
PC
if(mem8(abs16)bp=1),
PC+9+d7(label)+H
→
PC
if(mem8(abs16)bp=0), PC+9
→
PC
if(mem8(abs16)bp=1),
PC+10+d11(label)+H
→
PC
if(mem8(abs16)bp=0), PC+10
→
PC
0
→
PC.19 ~ 16, An
→
PC.15 ~ 0,
0
→
PC.H
abs18(label)+H
→
PC
abs20(label)+H
→
PC
SP-3
→
SP, (PC+3).bp7~0
→
mem8(SP),
(PC+3).bp15~8
→
mem8(SP+1),
(PC+3).H
→
mem8(SP+2).bp7,
0
→
mem8(SP+2).bp6~4,
(PC+3).bp19~16
→
mem8(SP+2).bp3~0,
0
→
PC.bp19~16,
An
→
PC.bp15~0, 0
→
PC.H
SP-3
→
SP, (PC+5).bp7~0
→
mem8(SP),
(PC+5).bp15~8
→
mem8(SP+1),
(PC+5).H
→
mem8(SP+2).bp7,
0
→
mem8(SP+2).bp6~4,
(PC+5).bp19~16
→
mem8(SP+2).bp3~0,
PC+5+d12(label)+H
→
PC
SP-3
→
SP, (PC+6).bp7~0
→
mem8(SP),
(PC+6).bp15~8
→
mem8(SP+1),
(PC+6).H
→
mem8(SP+2).bp7,
0
→
mem8(SP+2).bp6~4,
(PC+6).bp19~16
→
mem8(SP+2).bp3~0,
PC+6+d16(label)+H
→
PC
SP-3
→
SP, (PC+7).bp7~0
→
mem8(SP),
(PC+7).bp15~8
→
mem8(SP+1),
(PC+7).H
→
mem8(SP+2).bp7,
0
→
mem8(SP+2).bp6~4,
(PC+7).bp19~16
→
mem8(SP+2).bp3~0,
abs18(label)+H
→
PC
SP-3
→
SP, (PC+9).bp7~0
→
mem8(SP),
(PC+9).bp15~8
→
mem8(SP+1),
(PC+9).H
→
mem8(SP+2).bp7,
0
→
mem8(SP+2).bp6~4,
(PC+9).bp19~16
→
mem8(SP+2).bp3~0,
abs20(label)+H
→
PC
TBZ (abs16)bp, label
TBZ (abs16)bp, label
TBNZ (abs8)bp, label
TBNZ (abs8)bp, label
TBNZ (io8)bp, label
TBNZ (io8)bp, label
TBNZ (abs16)bp, label
TBNZ (abs16)bp, label
JMP (An)
JMP label
JMP label
JSR (An)
JSR label
JSR label
JSR label
JSR label
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
z
z
z
z
z
z
z
z
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
z
z
z
z
z
z
z
z
-
-
-
-
-
-
-
-
TBZ
TBNZ
JMP
JSR
Group
REP
Notes
Operation
VF NF CF ZF
Code
Size
Execution
Cycle
Machine Code
MN101L SERIES INSTRUCTION SET
Flag
*4 d12 sign-extention
*5 d16 sign-extention
*6 aa=abs18.17~16
*7 B=abs20.19
*8 bbb=abs20.18~16
*1 d7 sign-extention
*2 d11 sign-extention
*3 not branch / branch
Summary of Contents for MN101L Series
Page 1: ...Cover MICROCOMPUTER MN101L MN101LR05D 04D 03D 02D LSI User s Manual Pub No 21705 015E ...
Page 2: ......
Page 8: ......
Page 10: ......
Page 11: ...Contents Contents 0 ...
Page 22: ... Contents 11 ...
Page 23: ...I Chapter 1 Overview 1 ...
Page 62: ...Chapter 1 Overview I 40 Cautions for Circuit Setup ...
Page 63: ...II Chapter 2 CPU 2 ...
Page 94: ...Chapter 2 CPU II 32 Reset ...
Page 95: ...III Chapter 3 Interrupts 3 ...
Page 143: ...IV Chapter 4 Clock Mode Voltage Control 4 ...
Page 175: ...V Chapter 5 Watchdog Timer WDT 5 ...
Page 180: ...Chapter 5 Watchdog Timer WDT V 6 Operation ...
Page 181: ...VI Chapter 6 Power Supply Voltage Detection 6 ...
Page 189: ...VII Chapter 7 I O Port 7 ...
Page 248: ...Chapter 7 I O Port VII 60 Port 8 ...
Page 249: ...VIII Chapter 8 8 bit Timer 8 ...
Page 282: ...Chapter 8 8 bit Timer VIII 34 8 bit Timer Cascade Connection ...
Page 283: ...IX Chapter 9 16 bit Timer 9 ...
Page 346: ...Chapter 9 16 bit Timer IX 64 IGBT Output with Dead Time ...
Page 347: ...X Chapter 10 General Purpose Time Base Free Running Timer 10 ...
Page 361: ...XI Chapter 11 RTC Time Base Timer RTC TBT 11 ...
Page 371: ...XII Chapter 12 Real Time Clock RTC 12 ...
Page 389: ...XIII Chapter 13 Serial Interface 13 ...
Page 458: ...Chapter 13 Serial Interface XIII 70 IIC Communication ...
Page 459: ...XIV Chapter 14 DMA Controller 14 ...
Page 472: ...Chapter 14 DMA Controller XIV 14 DMA Data Transfer ...
Page 473: ...XV Chapter 15 Buzzer 15 ...
Page 479: ...XVI Chapter 16 A D Converter ADC 16 ...
Page 493: ...XVII Chapter 17 LCD 17 ...
Page 530: ...Chapter 17 LCD XVII 38 LCD Display Examples ...
Page 531: ...XVIII Chapter 18 ReRAM 18 ...
Page 538: ...Chapter 18 ReRAM XVIII 8 Command Library ...
Page 539: ...XIX Chapter 19 On Board Debugger 19 ...
Page 542: ...Chapter 19 On Board Debugger XIX 4 List of on board debugging functions ...
Page 543: ...XX Chapter 20 Appendix 20 ...