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Panasonic MN101L Series, User Manual

The Panasonic MN101L Series, an innovative electronic device, comes with a comprehensive User Manual that provides detailed instructions on setup and optimal usage. You can conveniently download the manual for free from manualshive.com, ensuring you have all the necessary information at your fingertips.

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Chapter 13

Serial Interface

Clock-Synchronous Communication

XIII - 41

13.3.4

Setting Procedure

Refer to the following pages for the setting procedure in clock synchronous mode.

Setting

Page

Initial setting before communication

XIII-42

Data transmission/reception (1-byte communication mode)

XIII-43

Data transmission (1-byte communication mode)

XIII-43

Data reception (1-byte communication mode)

XIII-44

Data transmission/reception (consecutive communication mode)

XIII-44

Data transmission (consecutive communication mode)

XIII-45

Data reception (consecutive communication mode)

XIII-45

Summary of Contents for MN101L Series

Page 1: ...Cover MICROCOMPUTER MN101L MN101LR05D 04D 03D 02D LSI User s Manual Pub No 21705 015E ...

Page 2: ......

Page 3: ...products and product specifications described in this book are subject to change without notice for modification and or im provement At the final stage of your design purchasing or use of the products therefore ask for the most up to date Product Standards in advance to make sure that the latest specifications satisfy your requirements 5 When designing your equipment comply with the range of absol...

Page 4: ...ter Hint chapter 2 Basic CPU I I 4 8 Reset 2 8 Reset 2 8 1 Reset operation the CPU contents are reset and registers are intialized when the NRST pin P 27 is pulled to low Initiating a Reset There are two methods to initiate areset 1 Drive the NRST pin low for at least four clock cycles NTST pin should be holded low for more than 4 clock cycles 200 ns a t a 20 NHz Figure 2 8 1 MInimum Reset PUlse W...

Page 5: ...ding to the description in this item Register name Register specification Chapter15 8 bit Timer Each item is explained below Timer 0 Mode Register TM0MD 0x0A200 8 bit Access Register 15 2 3 Timer Mode Registers Values of the timer mode register contorl the operation initialization and clock source selection of each timer For setting clock sources refer to 15 3 Clock Source Selection Register symbo...

Page 6: ...e Describes the installation commands and options of the C Compiler MN101C MN101E Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler MN101C MN101E Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler MN101C MN101E Series Cross assembler User s Manual Describes the assembler syntax and notation PanaX EX Installat...

Page 7: ... Voltage Control Chapter 5 Watchdog Timer WDT Chapter 6 Power Supply Voltage Detection Chapter 7 I O Port Chapter 8 8 bit Timer Chapter 9 16 bit Timer Chapter 10 General Purpose Time Base Free Running Timer Chapter 11 RTC Time Base Timer RTC TBT Chapter 12 Real Time Clock RTC 0 1 2 3 4 5 6 7 8 9 10 11 12 ...

Page 8: ......

Page 9: ...apter 13 Serial Interface Chapter 14 DMA Controller Chapter 15 Buzzer Chapter 16 A D Converter ADC Chapter 17 LCD Chapter 18 ReRAM Chapter 19 On Board Debugger Chapter 20 Appendix 13 14 15 16 17 18 19 20 ...

Page 10: ......

Page 11: ...Contents Contents 0 ...

Page 12: ... Package Dimension I 31 1 6 Cautions for Circuit Setup I 35 1 6 1 Usage Notes I 35 1 6 2 Unused Pins I 36 1 6 3 Power Supply I 38 1 6 4 Power Supply Circuit I 39 Chapter 2 CPU II 1 2 1 Overview II 2 2 1 1 CPU Control Registers II 3 2 1 2 Data Registers D0 D1 D2 D3 II 3 2 1 3 Address Registers A0 A1 II 3 2 1 4 Stack Pointer SP II 4 2 1 5 Program Counter PC II 4 2 1 6 Processor Status Word PSW II 5 ...

Page 13: ...3 1 1 Block Diagram III 3 3 1 2 Operation III 4 3 1 3 Maskable Interrupt Control Register Setup III 15 3 1 4 Group Interrupt Control Register Setup III 17 3 2 Control Registers III 20 3 2 1 Non maskable Interrupt NMI Control Register III 22 3 2 2 External Interrupt Control Register III 23 3 2 3 Peripheral Group Interrupt Control Register III 24 3 2 4 Other Interrupt Control Register III 29 3 2 5 B...

Page 14: ... Operation V 4 5 3 2 Setup Example V 5 Chapter 6 Power Supply Voltage Detection VI 1 6 1 Overview VI 2 6 1 1 Power Supply Voltage Detection Overview VI 2 6 2 Control Register VI 3 6 2 1 Registers VI 3 6 2 2 Power Supply Voltage Detection Control Registers VI 4 6 3 Setting Example VI 7 6 3 1 PSVD Setting Example VI 7 Chapter 7 I O Port VII 1 7 1 Overview VII 2 7 1 1 I O Port Overview VII 2 7 2 Cont...

Page 15: ... O Port Functions VII 33 7 4 Port 0 VII 34 7 4 1 Setup of Port 0 VII 34 7 5 Port 1 VII 37 7 5 1 Setup of Port 1 VII 37 7 6 Port 2 VII 40 7 6 1 Setup of Port 2 VII 40 7 7 Port 3 VII 43 7 7 1 Setup of Port 3 VII 43 7 8 Port 4 VII 46 7 8 1 Setup of Port 4 VII 46 7 9 Port 5 VII 49 7 9 1 Setup of Port 5 VII 49 7 10 Port 6 VII 52 7 10 1 Setup of Port 6 VII 52 7 11 Port 7 VII 55 7 11 1 Setup of Port 7 VI...

Page 16: ... and Timer 4 VIII 29 8 7 2 Setup Example VIII 30 8 8 8 bit Timer Cascade Connection VIII 31 8 8 1 Operation VIII 31 8 8 2 Setup Example VIII 33 Chapter 9 16 bit Timer IX 1 9 1 Overview IX 2 9 2 16 bit Timer Control Registers IX 4 9 2 1 Programmable Timer Registers IX 6 9 2 2 Timer Mode Registers IX 10 9 3 16 bit Timer IX 21 9 3 1 Operation IX 21 9 3 2 Setup Example IX 24 9 4 16 bit Event Count IX ...

Page 17: ...apter 10 General Purpose Time Base Free Running Timer X 1 10 1 Overview X 2 10 1 1 Functions X 2 10 1 2 Block Diagram X 3 10 2 Control Registers X 4 10 2 1 Control Registers X 4 10 2 2 Programmable Timer Registers X 5 10 2 3 Timer 6 Enable Register X 6 10 2 4 Timer Mode Register X 7 10 3 8 bit Free running Timer X 8 10 3 1 Operation X 8 10 3 2 Setup Example X 11 10 4 Time Base Timer X 12 10 4 1 Op...

Page 18: ... 13 1 Overview XIII 2 13 1 1 Functions XIII 3 13 1 2 Block Diagram XIII 5 13 2 Control Registers XIII 7 13 2 1 Registers XIII 7 13 2 2 Input Output Pin Control Register XIII 9 13 2 3 Receive Data Buffer XIII 10 13 2 4 Transmit Data Buffer XIII 10 13 2 5 Mode Register XIII 11 13 2 6 Status Register XIII 19 13 2 7 Address Setting Register XIII 22 13 2 8 BRTM Operation Mode Setting Register XIII 22 1...

Page 19: ...ter XIV 9 14 2 3 DMA Destination Address Register XIV 10 14 2 4 DMA Transfer Word Count Register XIV 11 14 3 DMA Data Transfer XIV 12 14 3 1 Single Transfer Mode XIV 12 14 3 2 Burst Transfer Mode XIV 13 Chapter 15 Buzzer XV 1 15 1 Overview XV 2 15 2 Control Register XV 3 15 2 1 Registers XV 3 15 2 2 Buzzer Control Register XV 4 15 3 Operation XV 5 15 3 1 Operation XV 5 15 3 2 Setup Example XV 6 Ch...

Page 20: ...VOL and BSTVOL XVII 25 17 4 LCD Display Examples XVII 26 17 4 1 LCD Display Example static XVII 26 17 4 2 LCD Operation Setup Example static XVII 28 17 4 3 LCD Display Example 1 2 duty XVII 29 17 4 4 LCD Operation Setup 1 2 duty XVII 31 17 4 5 LCD Display Example 1 3 duty XVII 32 17 4 6 LCD Operation Setup 1 3 duty XVII 34 17 4 7 LCD Display Example 1 4 duty XVII 35 17 4 8 LCD Operation Setup 1 4 ...

Page 21: ...10 Chapter 19 On Board Debugger XIX 1 19 1 Overview XIX 2 19 2 List of on board debugging functions XIX 3 Chapter 20 Appendix XX 1 20 1 Symbol Definitions XX 2 20 2 Instruction set XX 5 20 3 Instruction map XX 11 ...

Page 22: ... Contents 11 ...

Page 23: ...I Chapter 1 Overview 1 ...

Page 24: ...ALT mode High Speed Low Speed mode STOP mode Embedded Memory ROM ReRAM 64 KB Programmable area 62 KB Data area 2 KB RAM 4 KB ReRAM Specification Program voltage VDD30 1 8 V to 3 6 V Program cycles 1 K Program area 100 K Data area Data is rewritable in bytes without data erase Clock Oscillator 4 circuits External Low Speed Oscillation SOSCCLK 32 768 kHz crystal or ceramic External High Speed Oscill...

Page 25: ...LK 4 HCLK 16 HCLK 32 HCLK 64 SCLK SYSCLK 2 SYSCLK 4 and TM0IO input Timer 1 Function Square wave output event count 16 bit cascade connection connected with Timer 0 Clock Source HCLK HCLK 4 HCLK 16 HCLK 64 HCLK 128 SCLK SYSCLK 2 SYSCLK 8 and TM1IO input Timer 2 Function Square wave output additional pulse PWM output event count simple pulse width measurement Clock Source HCLK HCLK 4 HCLK 16 HCLK 3...

Page 26: ...put event count and TM9IO RTC time base timer RTC TBT Function Clock generation for the Real Time Clock RTC Frequency correction Correction Range 488 ppm to 31220 ppm Accuracy approx 0 48 ppm to 30 52 ppm Clock Source SOSCCLK or SRCCLK Real Time Clock RTC Function Calendar calculation adjustment of leap year Periodic interrupt 0 5 s 1 s 1 min and 1 hour Alarm0 interrupt date month minute Alarm1 in...

Page 27: ...ble N channel transistor drive strength 55 pins MN101LR04D 53 pins selectable N channel transistor drive strength 41 pins MN101LR03D 37 pins selectable N channel transistor drive strength 27 pins MN101LR02D 22 pins selectable N channel transistor drive strength 19 pins Clock Output HCLK SCLK SYSCLK or RTCCLK can be output Automatic Reset Circuit Low voltage Detection Circuit LVI LCD Driver 43 segm...

Page 28: ...h halogen free Panasonic halogen free semiconductor products refer to the products made of molding resin and interposer which conform to the following standards Bromine 900 ppm Maximum Concentration Value Chlorine 900 ppm Maximum Concentration Value Bromine Chlorine 1500 ppm Maximum Concentration Value The above mentioned standards are based on the numerical value described in IEC61249 2 21 Antimo...

Page 29: ...rial communication pins SBO3 SDA3 SBT3 SCL3 SBI3 SBCS3 SBO3 SDA3 SBT3 SCL3 SBI3 SBCS3 SBO3 SDA3 SBT3 SCL3 SBO3 SDA3 SBT3 SCL3 SBI3 Clock synchronous 2 3 or 4 wire 2 3 or 4 wire 2 wire 2 or 3 wire SPI compatible 2 2 Buzzer Buzzer output Inverted buzzer output BUZ NBUZ BUZ NBUZ BUZ NBUZ NBUZ ADC Analog input 8 pins AN0 7 6 pins AN2 7 4 pins AN2 5 3 pins AN3 5 LCD driver Segment output 43 pins SEG0 4...

Page 30: ...SEG 29 SEG 30 SEG 20 Port3 SEG 28 SEG 29 SEG 30 SEG 31 SEG 32 SEG 33 SEG 34 SEG 35 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 Port4 SEG 20 SEG 21 SEG 22 SEG 23 SEG 24 SEG 25 SEG 26 SEG 27 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 Port5 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 ...

Page 31: ... 14 12 7 P06 TM8IOB SBI3A 15 13 P07 TM9IOA SBCS3A 16 P10 IRQ0A KEY0A AN0 17 P11 IRQ1A KEY1A AN1 18 14 10 P12 IRQ4C KEY2A AN2 19 15 11 8 P13 IRQ5C KEY3A AN3 20 16 12 9 VREFP 21 17 13 10 DMOD 22 18 14 11 OCD_CLK P14 IRQ4A KEY4A AN4 23 19 15 12 OCD_DATA P15 IRQ5A KEY5A AN5 24 20 P16 IRQ6A KEY6A AN6 25 21 P17 KEY7A AN7 26 22 P20 TM1IOB TM9IOB 27 23 P21 TM5IOA 28 P22 SBI2B 29 P23 SBO2B SDA2B 30 P24 SBT...

Page 32: ...3 IRQ3B 61 49 25 P64 KEY4B SBI0A RXD0A 62 50 26 P65 KEY5B SBO0A TXD0A 63 51 27 P66 KEY6B SBT0A 64 52 28 P67 KEY7B SBCS0A 65 53 37 P70 IRQ6B 66 54 38 P71 IRQ5B 67 55 39 P72 IRQ4B TM3IOB 68 56 40 P73 TM5IOB 69 P74 70 P75 71 P76 72 P77 73 57 41 C1 P82 74 58 42 C2 P83 75 59 43 VLC3 P84 76 60 44 VLC2 P85 77 61 45 VLC1 78 62 46 29 VDD30 79 63 47 30 VDD18 80 64 48 31 VDD11 Refer to Table 1 2 3 for LCD co...

Page 33: ...SEG9 IRQ2B P64 SEG7 SBI0A RXD0A KEY4B IRQ1A KEY1A AN1 P11 IRQ4C KEY2A AN2 P12 OCD_CLK IRQ4A KEY4A AN4 P14 OCD_DATA IRQ5A KEY5A AN5 P15 IRQ6A KEY6A AN6 P16 KEY7A AN7 P17 TM9IOB TM1IOB SEG42 P20 BUZA SEG32 P33 TM5IOA SEG41 P21 SBI2B SEG40 P22 SBO2B SDA2B SEG39 P23 P60 SEG11 IRQ0B P57 SEG12 TM8IOA KEY3B CLKOUTB TM8IOB SBI3A P06 TM7IOA SBO3A SDA3A P04 SBT2B SCL2B SEG38 P24 SBCS2B SEG37 P25 SBI1A RXD1A...

Page 34: ...KEY4A AN4 P14 OCD_DATA IRQ5A KEY5A AN5 P15 IRQ6A KEY6A AN6 P16 KEY7A AN7 P17 TM9IOB TM1IOB SEG30 P20 TM5IOA SEG29 P21 P60 SEG7 IRQ0B P57 SEG8 TM8IOA KEY3B CLKOUTB XI VSS P83 C2 P82 C1 P55 SEG10 TM1IOA KEY1B BUZA SEG24 P33 SBI1A RXD1A SEG28 P26 SBCS1A SEG25 P32 SBO1A TXD1A SEG27 P30 SBT1A SEG26 P31 SBI0B RXD0B SEG22 P35 SBT0B SEG20 P37 SBO0B TXD0B SEG21 P36 NBUZA TM4IOA TM7IOB SEG23 P34 TM8IOC TM2I...

Page 35: ...OB P71 COM2 IRQ5B P70 COM3 IRQ6B OCD_CLK IRQ4A KEY4A AN4 P14 OCD_DATA IRQ5A KEY5A AN5 P15 P60 SEG3 IRQ0B P57 SEG4 TM8IOA KEY3B CLKOUTB XI VSS P83 C2 P82 C1 P55 SEG6 TM1IOA KEY1B BUZA SEG16 P33 SBI1A RXD1A SEG20 P26 SBCS1A SEG17 P32 SBO1A TXD1A SEG19 P30 SBT1A SEG18 P31 SBI0B RXD0B SEG14 P35 SBT0B SEG12 P37 SBO0B TXD0B SEG13 P36 NBUZA TM4IOA TM7IOB SEG15 P34 TM7IOA SBO3A SDA3A P04 IRQ5C KEY3A AN3 P...

Page 36: ...7 NRST XO P56 TM3IOA KEY2B P67 SBCS0A KEY7B P66 SBT0A KEY6B P65 SBO0A TXD0A KEY5B P64 SBI0A RXD0A KEY4B TM8IOB SBI3A P06 OCD_CLK IRQ4A KEY4A AN4 P14 OCD_DATA IRQ5A KEY5A AN5 P15 P57 TM8IOA KEY3B CLKOUTB TM7IOA SBO3A SDA3A P04 VREFP XI VSS P55 TM1IOA KEY1B P44 SBCS2A P41 SBI2A P43 SBT2A SCL2A P42 SBO2A SDA2A SBI0B RXD0B P35 SBT0B P37 SBO0B TXD0B P36 NBUZA TM4IOA TM7IOB P34 CLKOUTA TM2IOA TM0IOA SBT...

Page 37: ...0 C1 C2 LCD voltage boost capacitor pin When using the internal LCD booster circuit connect the capacitor of 0 22 µF between C1 and C2 VREFP ADC Reference power supply pin When ADC is not used connect VREFP to VDD30 The voltage level of VREFP must be over 0 8 VDD30 at any time including LSI power on OSC1 OSC2 Input Output External high speed oscillation pin When the external high speed oscillation...

Page 38: ...2A No P13 AN3 IRQ5C KEY3A No P14 AN4 IRQ4A KEY4A OCD_CLK No P15 AN5 IRQ5A KEY5A OCD_DATA No P16 AN6 IRQ6A KEY6A No P17 AN7 KEY7A No P20 SEG42 TM1IOB TM9IOB Input Output Yes Port 2 At each port the I O direction and the pull up resistor connection is controlled individually At LSI reset each pin is set to input mode and the pull up resistor is not connected The drive strength of output Nch transist...

Page 39: ... Port 6 At each port the I O direction and the pull up resistor connection is controlled individually At LSI reset each pin is set to input mode and the pull up resistor is not connected The drive strength of output Nch transistor can be changed P61 SEG10 IRQ1B Yes P62 SEG9 IRQ2B Yes P63 SEG8 IRQ3B Yes P64 SEG7 KEY4B SBI0A RXD0A Yes P65 SEG6 KEY5B SBO0A TXD0A Yes P66 SEG5 KEY6B SBT0A Yes P67 SEG4 ...

Page 40: ...ain by setting PnODC SBCS0A SBCS0B SBCS1A SBCS1B SBCS2A SBCS2B SBCS3A SBCS3B Input Output Serial chip select I O pins Pull up resistor can be added by setting PnPLUP Select the input or output mode by setting PnDIR Select the serial chip select I O by setting SCnMD3 SCnSBTS n 0 1 or SCnMD2 SCnSBCSEN n 2 3 TM0IOA TM0IOB TM1IOA TM1IOB TM2IOA TM2IOB TM3IOA TM3IOB TM4IOA TM4IOB TM5IOA TM5IOB TM7IOA TM...

Page 41: ...utput pin Select the buzzer output pin with BUZCNT NBUZA NBUZB Output Inverted Buzzer output pin Select the inverted buzzer output pin with BUZCNT CLKOUTA CLKOUTB Output Clock output pins Select the clkout pin with CLKOUT OCD_CLK OCD_DATA Input Output On board debugger I O pins These pins are used for on board debugging Pin name Input Output Description ...

Page 42: ...8 IOL2 avg 5 A10 All pins IOH avg 5 A11 Total output current for all pins 1 ITOL 60 A12 ITOH 60 A13 Power dissipation PT 230 Ta 85 C mW A14 Operating ambient temperature Topr 40 to 85 C A15 Storage temperature Tstg 55 to 125 1 The values are applied to any period of 100 ms 2 To stabilize the internal power supply voltage connect bypass capacitors as follows to at least one or more points close to ...

Page 43: ...r the internal low speed oscillation 8 tc1 2 When fSYSCLK is generated by using the internal high speed oscillation or the external high speed oscillation However for tc2 only by using the internal high speed oscillation tc3 When fSYSCLK is generated by using the internal low speed oscillation 9 When using auto reset function the lowest voltage is the auto reset detection voltage VDD30 VRSTL to 3 ...

Page 44: ... to 85 C 3 0 3 0 B15 Temperature Voltage dependence EF5 fHRCCLK 1 MHz Ta 40 C to 85 C 10 0 10 0 Internal low speed RC oscillation B16 Frequency FSRCCLK VDD30 VRSTL to 3 6 V 40 kHz B17 Temperature Voltage dependence EF6 Ta 40 C to 85 C 20 0 20 0 10 Output frequency of the internal high speed RC oscillation can be selected by setting the FCNT bit of HCLKCNT register Figure 1 4 1 High speed oscillati...

Page 45: ... Condition Limits Unit MIN TYP MAX External clock input 1 OSC1 OSC2 is open MN101LR02D is not applicable B18 Clock frequency fHOSCCLK 1 0 10 0 MHz B19 High period time 11 twh1 Figure 1 4 3 45 ns B20 Low period time 11 twl1 45 B21 Rise time twr1 Figure 1 4 3 5 0 B22 Fall time twf1 5 0 11 Set the clock duty ratio to the value from 45 to 55 twh1 twl1 0 9VDD30 twf1 twc1 twr1 0 1VDD30 ...

Page 46: ...RCCLK 10 MHz VDD30 3 0 V VDD18 1 8 V fSYSCLK fHRCCLK 2 1 3 0 C3 IDD3 fHRCCLK 8 MHz VDD30 3 0 V VDD18 1 8 V fSYSCLK fHRCCLK 1 72 2 5 C4 IDD4 fHRCCLK 8 MHz VDD30 3 0 V VDD18 1 8 V fSYSCLK fHRCCLK 2 0 94 1 5 C5 IDD5 fHOSCCLK 4 MHz VDD30 3 0 V VDD18 1 8 V fSYSCLK fHOSCCLK 0 84 1 3 C6 IDD6 fHRCCLK 1 MHz VDD30 3 0 V VDD18 1 3 V fSYSCLK fHRCCLK 0 22 0 36 C7 IDD7 fSOSCCLK 32 768 kHz VDD30 3 0 V VDD18 1 1 ...

Page 47: ...pins to the input mode VDD18 the Logic supply voltage to 1 3 V the oscillation mode to NORMAL the internal high oscillation 1 MHz fix the input pins to VDD30 level IDD7 Operating supply current After setting all input and output pins to the input mode VDD18 the Logic supply voltage to 1 1 V the oscillation mode to SLOW the external oscillation fix the input pins to VDD30 level and input the 32 768...

Page 48: ...3 0 V VI VSS with pull up resistor 30 100 300 kΩ C25 High level output voltage VOH3 VDD30 3 0 V IOH 2 0 mA 2 4 V C26 Low level output voltage VOL3 VDD30 3 0 V IOL 2 0 mA 0 4 Input Output pin 4 P00 to P07 P20 to P26 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 Schmitt input C27 High level input voltage VIH4 0 8VDD30 VDD30 V C28 Low level input voltage VIL4 0 0 2VDD30 C29 Input leakage cur...

Page 49: ...ge difference of output waveform VOSG VDD30 VLC1 3 0 V ISEG 2 µA 0 6 V LCD boost output pin 1 VLC1 VLC2 VLC3 VLC3 Triple output compared to the reference voltage output MN101LR02D is not applicable C39 Output voltage VLC1 VDD30 VRSTL to 3 0 V VLC3 1 0 V Ta 25 C LCD display OFF SEG COM with no load LCD boost clock 125 kHz 2 7 3 0 3 3 V C40 VLC2 1 8 2 0 2 2 C41 VLC3 0 9 1 0 1 1 VDD30 VRSTL to 3 6 V ...

Page 50: ...tial non linearity error DNL 3 D4 Zero voltage transition EZS 10 30 mV D5 full scale voltage transition EFS 2970 2990 D6 AD conversion time tCV fSYSCLK 8 MHz TAD 750 ns 15 38 µs D7 Sampling time tS TAD 750 ns 1 5 D8 Reference voltage VREFP VREFP VDD30 1 8 VDD30 V D9 Analog input voltage VAIN VSS VREFP D10 Analog input leakage current IAINL At channel off VADIN 0 V to VDD30 1 µA 13 TAD denotes the ...

Page 51: ...Auto reset voltage detection level VRSTH VDD30 Low High 1 10 1 23 1 35 E3 VRSTL VDD30 High Low 1 10 1 18 1 30 E4 Slope of voltage startup SLVDD30 1 0 V ms Power supply Detection E5 Detection error ELVI 2 0 2 0 E6 Detection voltage VLVI 1 05 1 15 1 25 V 1 10 1 20 1 30 1 15 1 25 1 35 1 20 1 30 1 40 1 25 1 35 1 45 1 30 1 40 1 50 1 40 1 50 1 60 1 50 1 60 1 70 1 60 1 70 1 80 1 70 1 80 1 90 1 80 1 90 2 ...

Page 52: ...ts Unit MIN TYP MAX F1 Supply voltage for programming VDDEW 1 8 3 6 V F2 Guaranteed number of rewriting 14 NUMw1 Program area 1000 time NUMw2 Data area 100000 F3 Data hold time THOLD 10 year 14 One cycle from elimination to writing is counted as the number of rewriting Even if the same block is rewritten only once rewrite of each of blocks is individually counted as a rewrite count ...

Page 53: ...Chapter 1 Overview Package Dimension I 31 1 5 Package Dimension Package code TQFP080 P 1212 Unit mm Figure 1 5 1 80 pin TQFP Package Dimension ...

Page 54: ...Chapter 1 Overview I 32 Package Dimension Package code TQFP064 P 1010 Unit mm Figure 1 5 2 64 pin TQFP Package Dimension ...

Page 55: ...Chapter 1 Overview Package Dimension I 33 Package code TQFP048 P 0707 Unit mm Figure 1 5 3 48 pin TQFP Package Dimension ...

Page 56: ...34 Package Dimension Package code HQFN032 A 0505 Unit mm Figure 1 5 4 32 pin HQFN Package Dimension This package dimension is subject to change Before using this product obtain product spec ifications from our sales offices ...

Page 57: ...nt etc Cautions for Operation 1 If the LSI is used close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Operation temperature should be well considered If the temperature is over the guaranteed value unexpected operation could be occurred 3 Operation voltage should be also well considered If the operation voltage is over the operati...

Page 58: ... level is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and becomes noise sources to the internal power supply Figure 1 6 2 Unused Pin only for input Figure 1 6 3 Structure and Characteristics of Input Inverter OPEN Output Pull up resistor Input Input pin Input Input pin Pull down resistor Input ...

Page 59: ...tween P27 and VSS the discharge diodes between P27 and VDD30 should be connected VREFP Set VREFP VDD30 NATRON Input Pull up the pin to VDD30 when auto reset function is disabled or pull down the pin to VSS when auto reset function is enabled with the resistor the value of which is typically between 10 kΩ and 100 kΩ DMOD Input Pull down the pin to VSS with the resistor the value of which is typical...

Page 60: ...put Pin Voltage Relation between Power Supply and Reset Input Voltage with Auto reset disable After the LSI turns on input the sufficient reset pin voltage to be recognized as the reset signal For more information refer to the 2 5 1 Reset function Figure 1 6 6 Power Supply and Reset Input Voltage Input Input protection resistance VDD30 Forward current generation P N Power supply voltage VDD30 Rese...

Page 61: ... high density So the power circuit should be designed taking into consideration of AC line noise ripple caused by LED driver An example of a circuit with VDD30 emitter follower type is shown below Figure 1 6 7 Power Circuit Example emitter follower type VSS Microcomputer VDD30 Set the noise filter capacitors closer to microcomputer power pins For noise filterring ...

Page 62: ...Chapter 1 Overview I 40 Cautions for Circuit Setup ...

Page 63: ...II Chapter 2 CPU 2 ...

Page 64: ...8 bit 4 Address 16 bit 2 Others SP 16 bits PC 21 bits PSW 8 bits Instructions Number of instructions 39 Addressing modes 9 Instruction length Basic portion 1 byte Min Extended portion 0 5 byte n 0 n 10 Basic performance Internal operating frequency Max 10 MHz Instruction execution Min 1 cycle Register to register operation Min 1 cycle Load Store Min 1 cycle Condition branch non branching 1 cycle b...

Page 65: ...ese registers are used as address pointers specifying data locations The initial value of An is 0x0000 Figure 2 1 2 Address Registers Symbol Address R W Register name Pages CPUM 0x03F00 R W CPU mode control register IV 4 MEMCTR 0x03F01 R W Memory control register II 16 CKCTR 0x03F04 R W Clock control register IV 6 AUCTR 0x03F07 W Extended calculation control register II 18 SBNKR 0x03F0A R W Bank r...

Page 66: ...ure 2 1 3 Stack Pointer 2 1 5 Program Counter PC This register gives the address of the currently executed instruction and the LSB shows the half byte 4 bit infor mation The value of vector table at the address of 0x04000 is stored in PC just after the LSI reset Figure 2 1 4 Program Counter SP 15 0 Stack Pointer PC 19 H Program Counter 0 ...

Page 67: ... to handle a signed value Overflow Detection VF VF is set to 1 when the operation results overflow as a signed value Otherwise overflow bit is set to 0 Over flow bit is used to handle a signed value bp 7 6 5 4 3 2 1 0 Bit name BKD MIE IM1 0 VF NF CF ZF At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 BKD Bank function control 0 Bank addressing is enabled 1 ...

Page 68: ...imited within the address of 0x00000 to 0x0FFFF At the interrupt occurrence BKD bit is set to 1 and the bank function is invalid When returning from the above interrupt procedure the set value of BKD is returned to the one which is set before the interrupt occurrence To enable the bank function in an interrupt service routine set the BKD to 0 before access ing to data Before setting the interrupt ...

Page 69: ... an area of 256 bytes beginning at 0x00000 that supports efficient accesses with RAM short addressing and an special function area of 256 bytes beginning at 0x03F00 that supports efficient accesses with I O short addressing Figure 2 1 5 Address Space 0x040C0 0x04080 0x04000 0x00100 0x01000 0x00000 0x04100 0x04900 128 B 64 B 64 KB BANK1 BANK0 16 KB 48 KB 0x10000 0x1FFFF 0x03000 256 B 256 B 0x03F00 ...

Page 70: ...initialized before using There s no guarantee of proper operation when an access is executed to the non imple mented space where a memory ROM RAM a special function register or others are not arranged Don t allocate the instruction code to a special function register area And this area cannot use as stack area ...

Page 71: ...n be used All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed There are 3 instructions that can use this mode MOV Dn HA MOVW DWn HA MOVW An HA Combining handy addressing with ...

Page 72: ...es the address using an address register with 8 bit displacement Specifies the address using an address register with 16 bit displacement Specifies the address using stack pointer with 4 bit displacement Specifies the address using stack pointer with 8 bit displacement Specifies the address using stack pointer with 16 bit displacement Specifies an 8 bit offset from the address 0x00000 Specifies an...

Page 73: ...o the stack area and restore them by software While bank function is valid regardless of bank setting please use the absolute addressing mode It is allocated for I O short instruction for data access from 0x03F00 to 0x03FFF For access to the memory space 0x13F00 to 0x13FFF please use the addressing mode expect absolute register indirect or register relative indirect Refer to Chapter 2 2 1 8 Addres...

Page 74: ... stack relative indirect instruction and bit manipulation instruction Refer to 2 1 8 Addressing Modes Bit manipulation instruction depends on the value of the SBNKR register both of for reading and writing bp 7 6 5 4 3 2 1 0 Bit name Reserved Reserved Reserved SBA0 At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 Always read as 0 3 1 Reserved Must be set to 0 0 S...

Page 75: ...A39 LCDATA40 LCDATA41 LCDATA42 0x03ECX P0NLC P2NLC P3NLC P4NLC P5NLC P6NLC P7NLC LCDMD4 Reserved 0x03EDX RTCCTR RTCSTR RTCCIRQ RTCAL0IR Q AL0IRQMI AL0IRQH AL0IRQW RTCAL1IR Q AL1IRQMI AL1IRQH AL1IRQD AL1IRQM O 0x03EEX RTCSD RTCMID RTCHD RTCWD RTCDD RTCMOD RTCYD TBTCNT0 TBTCNT1 TBTR TBTADJL TBTADJH 0x03EFX Reserved 0x03F0X CPUM MEMCTR WDCTR DLYCTR CKCTR HCLKCNT SCLKCNT AUCTR Reserved SBNKR DBNKR Res...

Page 76: ...s respectively The bus control block controls the parallel opera tion of instruction read and data access Figure 2 2 1 shows functional block diagram of the bus controller Figure 2 2 1 Functional Block Diagram of the Bus Controller Operand address MUX Internal ROM Internal RAM Instruction queue Interrupt bus Instruction input bus Data input bus Data output bus Interrupt control Program address Add...

Page 77: ...f ROM bus RAM bus peripheral extension bus C BUS Table 2 2 1 Bus access cycle Type of bus Access address Wait cycle Access cycle ROM bus 0x04000 to 0x040FF 0x04900 to 0x13FFF 0 1 0x04100 to 0x048FF 1 2 RAM bus 0x00000 to 0x00FFF 0 1 Peripheral extension bus C BUS 0x03000 to 0x03BFF 2 3 0x03C00 to 0x03FFF 0 1 ...

Page 78: ...R MIESET to 1 disables all maskable interrupts after the PSW MIE is set to 0 If MEMCTR MIESET is set to 1 when PSW MIE is 1 the operation can not be guaranteed bp 7 6 5 4 3 2 1 0 Bit name IVBM Reserved IRWE MIESET At reset 0 0 0 0 0 0 0 1 Access R R R W R W R R W R R W bp Bit name Description 7 6 Always read as 0 5 IVBM Base address specification for interrupt vector table 0 Interrupt vector base ...

Page 79: ... macro instruction MULW DW0 DW1 DW1 DW0 4 0 z 0 z 32 bit 16 bit division unsigned MOV 4 0x3F07 Extended calculation macro instruction DIVWU DW1 DW0 A0 DW0 DW1 21 z z 0 z BCD addition without carry MOV 16 0x3F07 Extended calculation macro instruction BCDADD D0 BCD D1 BCD D0 BCD 4 0 0 z z BCD addition with carry MOV 32 0x3F07 Extended calculation macro instruction BCDADDC D0 BCD D1 BCD PSW CF D0 BCD...

Page 80: ...ULU At reset 0 0 0 0 0 0 0 0 Access W W W W W W W W bp Bit name Description 7 AUBCDSUBC BCD subtraction with carry 0 Disabled 1 Enabled 6 AUBCDSUB BCD subtraction without carry 0 Disabled 1 Enabled 5 AUBCDADDC BCD addition with carry 0 Disabled 1 Enabled 4 AUBCDADD BCD addition without carry 0 Disabled 1 Enabled 3 Reserved Must be set to 0 2 AUDIVU Unsigned division execution 0 Disabled 1 Enabled ...

Page 81: ... not set several bits simultaneously Do not read AUCTR Do not access AUCTR by the bit manipulation instructions By writing the following C language you can avoid generation of data load instructions and bit manipulation instructions define AUBCDSUB c a b asm D0 b D1 a tmov 0x40 0x03F07 c D0 AUBCDSUB result in1 in2 ...

Page 82: ...stitution Remainder DW1 DW0 32 bit data high 16 bits in DW1 register and low 16 bits in DW0 register are stored Bit Changes Operation VF NF CF ZF Size Cycles Codes Size Cycles Codes Instruction format Changes of VF NF CF ZF of PSW Operation descrition Caution Size Cycles Codes the shortest are shows by using this order format with change with no change in always 0 in always 1 0 1 Read with caution...

Page 83: ...n DW0 register This extended calculation instruction is generated by the compiler for MN101L series by appointing an option mmuldivw When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 MULWU MOV 0x01 0x03F07 VF NF CF ZF 0 z 0 z Operation DW0 DW1 DW1 DW0 Multiplies the unsigned 16 bit value of DW0 register by the unsigned 16 bit value of DW1 register an...

Page 84: ... in DW0 reg ister This extended calculation instruction is generated by the compiler for MN101L series by appointing an option mmuldivw When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 MULW MOV 0x02 0x03F07 VF NF CF ZF 0 z 0 z Operation DW0 DW1 DW1 DW0 Multiplies the signed 16 bit value of DW0 register by the signed 16 bit value of DW1 register and ...

Page 85: ...truction is generated by the compiler for MN101L series by appointing an option mmuldivw When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 DIVWU MOV 0x04 0x03F07 VF NF CF ZF z z 0 z Operation DW1 DW0 A0 DW0 DW1 Divides the unsigned 32 bit value which is stored in the DW1 register upper 16 bit and DW0 register lower 16 bit by the unsigned 16 bit value...

Page 86: ...ster When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it the result is not guaranteed BCDADD MOV 0x10 0x03F07 VF NF CF ZF 0 0 z z Operation D0 BCD D1 BCD D0 BCD Adds the D0 register 8 bit and the D1 register 8 bit as the value of each two digit BCD and stores ...

Page 87: ... D0 register When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it the result is not guaranteed BCDADDC MOV 0x20 0x03F07 VF NF CF ZF 0 0 z z Operation D0 BCD D1 BCD PSW CF D0 BCD Adds the D0 register 8 bit and the D1 register 8 bit as the value of each two digit...

Page 88: ...ter the BCD correction to the D0 register When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it the result is not guaranteed BCDSUB MOV 0x40 0x03F07 VF NF CF ZF 0 0 z z Operation D0 BCD D1 BCD D0 BCD Subtracts the D0 register 8 bit and the D1 register 8 bit as t...

Page 89: ... bit after the BCD correction to the D0 register When this extended calculation instruction is executed the handy address HA is updated in 0x03F07 In this instruction do not enter the value that can not be represented in BCD If you enter it the result is not guaranteed BCDSUBC MOV 0x80 0x03F07 VF NF CF ZF 0 0 z z Operation D0 BCD D1 BCD PSW CF D0 BCD Subtracts the D0 register 8 bit and the D1 regi...

Page 90: ...ion This LSI has the following four types of reset factors Power on reset when the NATRON pin is tied to Low Power down reset when the NATRON pin is tied to Low Low level signal input to NRST pin Two consecutive WDT overflow The LSI starts up in SLOW mode ...

Page 91: ... it occurs is called the oscillation sta bilization wait time During reset internal registers and special function registers are initialized 2 After the oscillation stabilization wait time the internal reset is released and the CPU starts executing the pro gram the address of which is shown in the interrupt vector table at 0x04000 The internal RAM is not initialized at reset It needs to be initial...

Page 92: ... DLYCTR The value of the DLYCTR must be determined for stabilizing the HCLK oscillation In this situation the frequency of OSCSTBCLK is equal to half the of HCLK After the oscillation stabilization the CPU enters the NORMAL mode 3 When recovering from STOP1 mode the wait time can be varied with the DLYCTR The value of the DLYCTR must be determined for stabilizing the SCLK oscillation In this situa...

Page 93: ...nal low speed oscillation 100 µs or more bp 7 6 5 4 3 2 1 0 Bit name DLY3 0 At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 Always read as 0 3 0 DLY3 0 Oscillation stabilization wait cycle selection 0000 214 1 fOSCSTBCLK 0001 213 1 fOSCSTBCLK 0010 212 1 fOSCSTBCLK 0011 211 1 fOSCSTBCLK 0100 210 1 fOSCSTBCLK 0101 29 1 fOSCSTBCLK 0110 28 1 fOSCSTBCLK 0111 27 1 fOS...

Page 94: ...Chapter 2 CPU II 32 Reset ...

Page 95: ...III Chapter 3 Interrupts 3 ...

Page 96: ...gisters are described in 3 2 Control Registers which includes the interrupt request bit IR the inter rupt enable bit IE and the interrupt level bits LV1 0 IR is set to 1 by the corresponding interrupt trigger and cleared to 0 when the interrupt is accepted IR can also be set and cleared by software IE controls the interrupt occurrence and can be set and cleared only by software IE is valid when PS...

Page 97: ...5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Interrupt IRQNMI level deter mination IM1 IRQLVL 2 0 IM0 NMICR Vector 1 Vector 2 Vector N Vector 30 WDTOVF IRQ0ICR IE IR LV1 0 External interrupt 0 0 1 DEC 2 PERI1ICR 0 1 DEC 2 PSW CPU Undefined Instruction MIE LV1 0 Vector 29 Group 0 interrupt Group 1 interrupt PERI0ICR 0 1 DEC 2 LV1 0 ...

Page 98: ...I instruction to go back to the main program which had been executed before the interrupt was accepted Figure 3 1 2 Interrupt Processing Sequence xICR IR of maskable interrupt is cleared to 0 by hardware when the corresponding interrupt is accepted but NMICR IRQNPG NMICR IRQNWDG PERI0DT PERI0DT6 0 and PERI1DT PERI1DT 4 0 are not cleared to 0 by hardware and must be cleared by software Start Interr...

Page 99: ...140 Timer 7 compare 2 match interrupt TM7OC2ICR 0x03FF0 17 0x04044 0x00144 Timer 8 interrupt TM8ICR 0x03FF1 18 0x04048 0x00148 Timer 8 compare 2 match interrupt TM8OC2ICR 0x03FF2 19 0x0404C 0x0014C Timer 9 interrupt TM9ICR 0x03FF3 20 0x04050 0x00150 Timer 9 compare 2 match interrupt TM9OC2ICR 0x03FF4 21 0x04054 0x00154 Serial interface 0 reception interrupt SC0RICR 0x03FF5 22 0x04058 0x00158 Seria...

Page 100: ...V1 0 is less than PSW IM1 0 NMI is handled in priority to maskable interrupts Figure 3 1 3 Interrupt Priority Example Table 3 1 2 Relation between PSW IM1 0 and acceptable interrupts Mask Level PSW IM1 0 Priority Acceptable Interrupt IM1 IM0 Level 0 0 0 Highest NMI Level 1 0 1 NMI Maskable Interrupt of Level 0 Level 2 1 0 NMI Maskable Interrupt of Level 0 to 1 Level 3 1 1 Lowest NMI Maskable Inter...

Page 101: ... PSW MIE is 1 the above interrupt request is accepted 4 IR is cleared to 0 by hardware IE is not cleared by hardware Figure 3 1 4 Determination of Interrupt Acceptance After IR is set to 1 by an interrupt trigger at step 1 if the same interrupt trigger occurs during the time of above 2 4 steps the latter interrupt trigger is ignored 7 xICR VF IM1 BKD IM0 NF 7 0 PSW In the case of xICR LV1 0 PSW IM...

Page 102: ...ion is executed BKD and MIE is set to 1 PSW IM1 0 change when PSW IM1 0 is set by software the LSI is reset an maskable interrupt is accepted and the value of PSW IM1 0 changes to the value of xICR IL1 0 When RTI instruction executes PSW IM1 0 go back to the value of it before the interrupt acceptance NMI is accepted and PSW IM1 0 change to 00 When an interrupt is accepted PSW MIE changes as follo...

Page 103: ... IM1 0 5 PSW and PC i e the return address are saved to the stack PSW Address SP PC bit 7 to 0 Address SP 1 6 The remaining PC is saved to the stack PC bits 15 to 8 Address SP 2 PC bits 19 to 16 and H Address SP 3 7 HA is saved to the stack Lower half of HA Address SP 4 Upper half of HA Address SP 5 8 The hardware branches program to the address in the vector table Figure 3 1 5 Stack Operation dur...

Page 104: ...The following is the processing sequence invoked by RTI instruction 1 PSW are restored from the stack SP 2 PC i e the return address are restored from the stack SP 1 to SP 3 3 HA are restored from the stack SP 4 SP 5 4 SP is updated SP 6 SP 5 Jump to the program address of PC Registers such as data registers D0 D1 D2 D3 or address registers A0 A1 are not saved by hardware so save them onto the sta...

Page 105: ...ccurs LV1 0 00 IM1 0 00 When MIESET is 0 MIE is set to 0 When MIESET is 1 MIE is set to 1 Interrupt 2 occurs LV1 0 10 1 Interrupt 3 generated LV1 0 11 IM1 0 11 RTI Interrupt handler 2 IM1 0 11 2 MIE 0 IM1 0 00 Reset Accepted because LV1 0 IM1 0 and MIE 1 Not accepted because LV1 0 IM1 0 Interrupt acceptance cycle Interrupt acceptance cycle Interrupt 2 is not accepted because LV1 0 10 PSW IM1 0 00 ...

Page 106: ...le maskable interrupt is not occurred To enable the multiple interrupts occurrence set MEMCTR MIESET to 1 by software before accepting inter rupts or set PSW MIE to 1 by software in the interrupt handler Do not write access to xICR of maskable interrupts when PSW MIE is 1 When the multiple interrupt acceptance is enabled be careful not to happen stack overflow ...

Page 107: ... 0 00 Figure 3 1 7 Processing Sequence for Multiple Interrupts Interrupt 1 occurs LV1 0 10 Main Program PSW IM1 0 11 Interrupt handler 1 Interrupt handler 2 RTI IM1 0 10 MIE 1 Interrupt 2 occurs LV1 0 00 Accepted because MIE 1 and LV1 0 IM1 0 IM1 0 00 IM1 0 11 IM1 0 10 RTI Accepted because LV1 0 IM1 0 Restart interrupt handler 1 Interrupt acceptance cycle Interrupt acceptance cycle Parentheses ind...

Page 108: ...n Program NMI 1 occurs NMI 2 occurs Interrupt acceptance cycle Interrupt acceptance cycle NMI handler 1 NMI handler 2 Parentheses indicates hardware processing The multiple interrupts are not accepted during NMI handler After RTI instruction NMI 2 is accepted If the undefined instruction occurs the following processing is not guaranteed 1 If the request of NMI 1 is not cleared NMI 1 is accepted ag...

Page 109: ... such as interrupt edge selection or timer interrupt cycle change 3 Permission settings of multiple interrupt MEMCTR MIESET 3 Set the permission of multiple interrupt Multiple interrupt is allowed when MIESET is set to 1 4 Enable the write interrupt request bit MEMCTR IRWE 1 4 Set MEMCTR IRWE to enable IR to be rewritten which is needed only when IR is changed by software 5 Rewrite the interrupt r...

Page 110: ...pt when writing xICR IR by software The interrupt request may be cleared when operating xICR by software while the MEM CTR IRWE is 1 For example when the bit operation to xICR is executed xICR is read modified and overwritten by CPU the interrupt request which occurs during the above read to write cycle is cleared because IR is overwritten with 0 by software To avoid this set MEMCTR IRWE to 0 whic...

Page 111: ...f PERInDT is changed as the following table When clearing all bits of the PERInDT read the value of PERInDT first and then write the same value to PERInDT Each bit of PERInDT is not cleared by hardware and needs to be cleared by software Don t change the bit of PERInICR while the corresponding bit of the PERInEN and the PER InDT is 1 When changing PERInICR the interrupt may be accepted unintention...

Page 112: ...is changed 2 Clear PERInDT PERI0DT PRI1DT 2 Clear PERInDT by reading the value of PERInDT and setting the register to it When operating the interrupts that occurred before this setting please don t clear the applicable bits 3 Set PERInEN PERI0EN PERI1EN 3 Enable the interrupt occurrence 4 Set the interrupt level PERInICR PERI0ICR PERI1ICR 4 Set the interrupt level by PERInICR PERInLV1 0 5 Enable a...

Page 113: ...ng to bit0 is executed Load the value of PERInDT to Dn and clear the PERInDT mov PERInEN Dm and Dm Dn Extract the request bit that interrupt is enabled Routine of bit0 factor btst 0x02 Dn beq bit1_end bit1_end interrupt program corresponding to bit1 When bit1 is set to 1 the interrupt program corresponding to bit1 is executed Routine of bit1 factor btst 0x80 Dn beq bit7_end bit7_end interrupt prog...

Page 114: ...atch interrupt control register III 29 TM8ICR 0x03FF1 R W Timer 8 interrupt control register III 29 TM8OC2ICR 0x03FF2 R W Timer 8 compare 2 match interrupt control register III 29 TM9ICR 0x03FF3 R W Timer 9 interrupt control register III 29 TM9OC2ICR 0x03FF4 R W Timer 9 compare 2 match interrupt control register III 29 SC0RICR 0x03FF5 R W Serial interface 0 reception interrupt control register III...

Page 115: ...ontrol Registers III 21 Write access to xICR must be done when PSW MIE is 0 There s no guarantee of proper operation if xICR is written with when PSW MIE is 1 When an xICR LV1 0 is set to 11 the interrupt IRQ does not occur ...

Page 116: ... Before RTI instruction is executed in the NMI interrupt handler they must be cleared IRQNWDG is not cleared by hardware Before RTI instruction is executed in the NMI inter rupt handler they must be cleared bp 7 6 5 4 3 2 1 0 Bit name IRQNPG IRQNWDG Reserved At reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W bp Bit name Description 7 3 Always read as 0 2 IRQNPG Detection of Undefined instructio...

Page 117: ...5 REDG Interrupt trigger edge 0 Falling edge 1 Rising edge 4 Always read as 0 3 Reserved Must be set to 0 2 Always read as 0 1 IE Interrupt enable control 0 Disable 1 Enable 0 IR Interrupt request detection 0 Not detected 1 Detected bp 7 6 5 4 3 2 1 0 Bit name LV1 LV0 Reserved IE IR At reset 0 0 0 0 0 0 0 0 Access R W R W R W R R W R R W R W bp Bit name Description 7 6 LV1 0 Interrupt level Set in...

Page 118: ...p 1 Interrupt Level Control Register PERI0ICR PERI1ICR bp 7 6 5 4 3 2 1 0 Bit name LV1 LV0 Reserved At reset 0 0 0 0 0 0 0 0 Access R W R W R R R W R R R bp Bit name Description 7 6 LV1 0 Interrupt level bit Set interrupt level from 0 to 3 5 4 Always read as 0 3 Reserved Must be set to 0 2 0 Always read as 0 ...

Page 119: ...ption 7 Always read as 0 6 EN6 RTC Alarm1 interrupt enable control 0 Disable 1 Enable 5 EN5 RTC Alarm0 interrupt enable control 0 Disable 1 Enable 4 EN4 RTC interrupt enable control 0 Disable 1 Enable 3 EN3 RTC TBT interrupt enable control 0 Disable 1 Enable 2 EN2 TBT interrupt enable control 0 Disable 1 Enable 1 EN1 Timer6 interrupt enable control 0 Disable 1 Enable 0 EN0 Timer5 interrupt enable ...

Page 120: ...Alarm1 interrupt request detection 0 Not detected 1 Detected 5 DT5 RTC Alarm0 interrupt request detection 0 Not detected 1 Detected 4 DT4 RTC interrupt request detection 0 Not detected 1 Detected 3 DT3 RTC TBT interrupt request detection 0 Not detected 1 Detected 2 DT2 TBT interrupt request detection 0 Not detected 1 Detected 1 DT1 Timer6 interrupt request detection 0 Not detected 1 Detected 0 DT0...

Page 121: ... Access R R R R W R W R W R W R W bp Bit name Description 7 5 Always read as 0 4 EN4 DMA Error interrupt enable control 0 Disable 1 Enable 3 EN3 DMA AddReq interrupt enable control 0 Disable 1 Enable 2 EN2 DMA interrupt enable control 0 Disable 1 Enable 1 EN1 A D interrupt enable control 0 Disable 1 Enable 0 EN0 LVD interrupt enable control 0 Disable 1 Enable ...

Page 122: ... R W R W bp Bit name Description 7 5 Always read as 0 4 DT4 DMA Error interrupt request detection 0 Not detected 1 Detected 3 DT3 DMA AddReq interrupt request detection 0 Not detected 1 Detected 2 DT2 DMA interrupt request detection 0 Not detected 1 Detected 1 DT1 A D interrupt request detection 0 Not detected 1 Detected 0 DT0 LVD interrupt request detection 0 Not detected 1 Detected ...

Page 123: ...n of above other interrupt control registers is described below bp 7 6 5 4 3 2 1 0 Bit name LV1 LV0 Reserved IE IR At reset 0 0 0 0 0 0 0 0 Access R W R W R R R W R R W R W bp Bit name Description 7 6 LV1 0 Interrupt level Set interrupt level from 0 to 3 5 4 Always read as 0 3 Reserved Must be set to 0 2 Always read as 0 1 IE Interrupt enable control 0 Disable 1 Enable 0 IR Interrupt request detec...

Page 124: ...0DT DT0 0 6 edge detection Timer 5 interrupt Timer 6 interrupt TBT interrupt RTC TBT interrupt RTC interrupt RTC Alarm0 interrupt RTC Alarm1 interrupt Group Interrupt 0 edge detection edge detection edge detection edge detection edge detection edge detection When the interrupt factor and set clear by software ocurred at the same time set clear by software is given priority PERI0DT DT1 PERI0DT DT2 ...

Page 125: ...LVD interrupt A D interrupt DMA interrupt DMA Addreq interrupt DMA Error interrupt Group Interrupt 1 When the interrupt factor and set clear by software ocurred at the same time set clear by software is given priority edge detection edge detection edge detection edge detection edge detection PERI1DT DT1 PERI1DT DT2 PERI1DT DT3 PERI1DT DT4 ...

Page 126: ...d interrupt Both edge triggered interrupt Noise filter Key interrupt IRQ0 P10 IRQ0A P60 IRQ0B IRQ1 P11 IRQ1A P61 IRQ1B IRQ2 P80 IRQ2A P62 IRQ2B IRQ3 P81 IRQ3A P63 IRQ3B IRQ4 P14 IRQ4A P72 IRQ4B P12 IRQ4C IRQ5 P15 IRQ5A P71 IRQ5B P13 IRQ5C IRQ6 P16 IRQ6A P70 IRQ6B IRQ7 P10 KEY0A P11 KEY1A P12 KEY2A P13 KEY3A P14 KEY4A P15 KEY5A P16 KEY6A P17 KEY7A P54 KEY0B P55 KEY1B P56 KEY2B P57 KEY3B P64 KEY4B P...

Page 127: ...selection register 0 III 36 EDGDT 0x03FD4 R W Both edges interrupt control register III 38 NFCTR23 0x03ED1 R W Noise filter 23 control register III 39 IRQ3 IRQ3ICR 0x03FE5 R W External interrupt 3 control register III 23 IRQIEN 0x03F4C R W External interrupt input control register III 35 IRQISEL0 0x03F4D R W External interrupt input pin selection register 0 III 36 EDGDT 0x03FD4 R W Both edges inte...

Page 128: ...er 0 III 36 EDGDT 0x03FD4 R W Both edges interrupt control register III 38 NFCTR67 0x03ED3 R W Noise filter 67 control register III 39 IRQ7 IRQ7ICR 0x03FE9 R W External interrupt 7 control register III 23 KEYSEL 0x03F4F R W KEY interrupt input pin selection register III 43 KEYIEN 0x03F4E R W KEY interrupt input control register III 44 NFCTR67 0x03FD3 R W Noise filter 67 control register III 39 Ext...

Page 129: ...s 0 6 IRQI6EN IRQ6 input enable control 0 Disable 1 Enable IRQ6A IRQ6B 5 IRQI5EN IRQ5 input enable control 0 Disable 1 Enable IRQ5A IRQ5B IRQ5C 4 IRQI4EN IRQ4 input enable control 0 Disable 1 Enable IRQ4A IRQ4B IRQ4C 3 IRQI3EN IRQ3 input enable control 0 Disable 1 Enable IRQ3A IRQ3B 2 IRQI2EN IRQ2 input enable control 0 Disable 1 Enable IRQ2A IRQ2B 1 IRQI1EN IRQ1 input enable control 0 Disable 1 E...

Page 130: ... R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 IRQ6SEL IRQ6 pin selection 0 IRQ6A P16 1 IRQ6B P70 5 IRQ5SEL IRQ5 pin selection 0 IRQ5A P15 1 IRQ5B P71 4 IRQ4SEL IRQ4 pin selection 0 IRQ4A P14 1 IRQ4B P72 3 IRQ3SEL IRQ3 pin selection 0 IRQ3A P81 1 IRQ3B P63 2 IRQ2SEL IRQ2 pin selection 0 IRQ2A P80 1 IRQ2B P62 1 IRQ1SEL IRQ1 pin selection 0 IRQ1A P11 1 IRQ1B P61 0 IRQ0SEL IRQ0 pin...

Page 131: ...RQISEL1 bp 7 6 5 4 3 2 1 0 Bit name IRQ5C SEL IRQ4C SEL At reset 0 0 0 0 0 0 0 0 Access R R R W R W R R R R bp Bit name Description 7 6 Always read as 0 5 IRQ5CSEL IRQ5 pin selection 0 IRQ5A IRQ5B P15 P71 1 IRQ5C P13 4 IRQ4CSEL IRQ4 pin selection 0 IRQ4A IRQ4B P14 P72 1 IRQ4C P12 3 0 Always read as 0 ...

Page 132: ...es Rising and falling edges 5 EDGSEL5 IRQ5 trigger selection 0 Rising edge or falling edge 1 Both edges Rising and falling edges 4 EDGSEL4 IRQ4 trigger selection 0 Rising edge or falling edge 1 Both edges Rising and falling edges 3 EDGSEL3 IRQ3 trigger selection 0 Rising edge or falling edge 1 Both edges Rising and falling edges 2 EDGSEL2 IRQ2 trigger selection 0 Rising edge or falling edge 1 Both...

Page 133: ...it name Description 7 5 NF1SCK2 NF1SCK1 NF1SCK0 IRQ1 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 4 NF1EN IRQ1 noise filter operation 0 Disabled 1 Enabled 3 1 NF0SCK2 NF0SCK1 NF0SCK0 IRQ0 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 0 NF0EN I...

Page 134: ...it name Description 7 5 NF3SCK2 NF3SCK1 NF3SCK0 IRQ3 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 4 NF3EN IRQ3 noise filter operation 0 Disabled 1 Enabled 3 1 NF2SCK2 NF2SCK1 NF2SCK0 IRQ2 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 0 NF2EN I...

Page 135: ...it name Description 7 5 NF5SCK2 NF5SCK1 NF5SCK0 IRQ5 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 4 NF5EN IRQ5 noise filter operation 0 Disabled 1 Enabled 3 1 NF4SCK2 NF4SCK1 NF4SCK0 IRQ4 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 0 NF4EN I...

Page 136: ...it name Description 7 5 NF7SCK2 NF7SCK1 NF7SCK0 IRQ7 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 4 NF7EN IRQ7 noise filter operation 0 Disabled 1 Enabled 3 1 NF6SCK2 NF6SCK1 NF6SCK0 IRQ6 noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 0 NF6EN I...

Page 137: ...R W bp Bit name Description 7 KEYSEL7 KEY7 pin selection 0 KEY7A P17 1 KEY7B P67 6 KEYSEL6 KEY6 pin selection 0 KEY6A P16 1 KEY6B P66 5 KEYSEL5 KEY5 pin selection 0 KEY5A P15 1 KEY5B P65 4 KEYSEL4 KEY4 pin selection 0 KEY4A P14 1 KEY4B P64 3 KEYSEL3 KEY3 pin selection 0 KEY3A P13 1 KEY3B P57 2 KEYSEL2 KEY2 pin selection 0 KEY2A P12 1 KEY2B P56 1 KEYSEL1 KEY1 pin selection 0 KEY1A P11 1 KEY1B P55 0...

Page 138: ...rol 0 Disable 1 Enable KEY7A KEY7B 6 KEY6EN KEY6 input enable control 0 Disable 1 Enable KEY6A KEY6B 5 KEY5EN KEY5 input enable control 0 Disable 1 Enable KEY5A KEY5B 4 KEY4EN KEY4 input enable control 0 Disable 1 Enable KEY4A KEY4B 3 KEY3EN KEY3 input enable control 0 Disable 1 Enable KEY3A KEY3B 2 KEY2EN KEY2 input enable control 0 Disable 1 Enable KEY2A KEY2B 1 KEY1EN KEY1 input enable control ...

Page 139: ... falling edge or both edges rising edge and falling edge of IRQn must be changed when IRQnICR IE is 0 After the interrupt edge is changed IRQnICR IR must be cleared before setting IRQnICR IE is 1 Step Settings Register Description 1 Set P72 as IRQ4 pin IRQIEN IRQISEL0 IRQISEL1 Set IRQIEN IRQ4EN to 1 Set IRQISEL0 IRQ4SEL to 1 Set IRQISEL1 IRQ4CSEL to 0 2 Select the rising edge triggered IRQ4 IRQ4IC...

Page 140: ... edges rising edge and falling edge of IRQn must be changed when IRQnICR IE is 0 After the interrupt edge is changed IRQnICR IR must be cleared before setting IRQnICR IE is 1 Step Settings Register Description 1 Set P10 as IRQ0 pin IRQIEN IRQISEL0 Set IRQIEN IRQ0EN to 1 Set IRQISEL0 IRQ0SEL to 0 Set P10 as the IRQ0 pin 2 Select the both edges triggered IRQ0 EDGDT Set EDGDT EDGDT0 to 1 3 Set the In...

Page 141: ...ree times and the level of it is not changed the signal can pass through NF Figure 3 3 1 Eliminating input noise at IRQn with NF NF cannot be used in STOP or HALT mode When an IRQn is used as the trigger to return from the STOP or HALT mode NF of the IRQn must not be used Step Settings Register Description 1 Set the input direction of P10 P11 P12 and P13 P1DIR Set P1DIR P1DIR3 0 to 0000 2 Add the ...

Page 142: ...nterrupt Step Settings Register Description 1 Set P10 as IRQ0 pin IRQIEN IRQISEL0 Set IRQIEN IRQ0EN to 1 Set IRQISEL0 IRQ0SEL to 0 Set P10 as the IRQ0 pin 2 Select the positive edge triggered IRQ0 IRQ0ICR Set IRQ0ICR REDG0 to 1 3 Activate NF of IRQ0 NFCTR01 Set NFCTR01 NF0EN to 1 4 Set the Interrupt level of IRQ0 IRQ0ICR Set IRQ0ICR LV1 0 as you like IRQ0ICR IR should be set to 0 5 Enable IRQ0 IRQ...

Page 143: ...IV Chapter 4 Clock Mode Voltage Control 4 ...

Page 144: ...necting crystal or ceramic oscillator to OSC1 OSC2 pins Internal low speed oscillation circuit 40 kHz clock SRCCLK can be generated External low speed oscillation circuit Low speed clock is generated by connecting crystal oscillator to XI XO pins M U X M U X HCLK High speed Clock SYSCLK System Clock HSCLK HSCLK Divider External High speed Oscillation HOSCCLK Internal High speed Oscillation HRCCLK ...

Page 145: ...name Page CPUM 0x03F00 R W CPU mode control register IV 4 CKCTR 0x03F04 R W System clock control register IV 6 HCLKCNT 0x03F05 R W High speed oscillation clock control register IV 7 SCLKCNT 0x03F06 R W Low speed oscillation clock control register IV 8 PRICKCNT0 0x03E10 R W Clock supply control register 0 IV 9 PRICKCNT1 0x03E11 R W Clock supply control register 1 IV 10 PRICKCNT2 0x03E12 R W Clock s...

Page 146: ...hanging CPUM or CKCTR The instruction for changing the data of CPUM or CKCTR must not be executed in the inter nal RAM bp 7 6 5 4 3 2 1 0 Bit name STOP HALT HALTMOD XIMOD OSCMOD CLKSEL Initial value 0 0 0 0 0 1 0 0 Access R R R W R W R W R W R W R W bp Bit name Description 7 6 Always read as 00 5 STOP STOP mode request 0 not STOP mode 1 STOP mode 4 HALT HALT mode request 0 not HALT mode 1 HALT mod...

Page 147: ...tus STOP HALT HALTMOD XIMOD OSCMOD CLKSEL HCLK SCLK System clock CPU NORMAL 0 0 0 1 1 1 Active Stop Active HCLK Active IDLE 0 0 1 1 0 Active Active SCLK Active SLOW 0 0 1 0 0 Stop Active SCLK Active HALT0 0 1 0 1 1 1 Active Stop Active HCLK Stop HALT1 0 1 0 1 0 1 0 Stop Active SCLK Stop HALT2 0 1 1 0 1 Stop Active Stop Stop HALT3 0 1 1 1 0 0 Stop Active Stop Stop STOP0 1 0 0 1 1 1 Stop Stop Stop S...

Page 148: ...ng CPUM or CKCTR The instruction for changing the data of CPUM or CKCTR must not be executed in the inter nal RAM bp 7 6 5 4 3 2 1 0 Bit name OSCSEL2 0 Initial value 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W bp Bit name Description 7 3 Always read as 00000 2 0 OSCSEL2 0 The frequency of SYSCLK 000 fHSCLK 001 fHSCLK 2 010 fHSCLK 4 011 fHSCLK 8 100 fHSCLK 16 101 fHSCLK 32 110 Setting is prohibite...

Page 149: ... R W R W R W R W bp Bit name Description 7 HCLKSEL High speed oscillation clock select 0 Internal high speed oscillation 1 External high speed oscillation Select internal high speed oscillation set the bit from 1 to 0 when HRC CNT 1 6 5 FCNT1 0 Internal High speed oscillation frequency select 00 1 MHz 01 Setting is prohibited 10 8 MHz 11 10 MHz 4 Always read as 0 3 2 Reserved Always set to 111 1 H...

Page 150: ...ow speed oscillation two cycles of the internal low speed oscillation When changing the SCLKSEL in Slow mode the above wait time is not needed bp 7 6 5 4 3 2 1 0 Bit name SCLKSEL Reserved SOSCCNT SRCCNT Initial value 0 0 0 0 0 1 1 1 Access R W R R R R R W R W R W bp Bit name Description 7 SCLKSEL Low speed oscillation clock select 0 Internal low speed oscillation 1 External low speed oscillation 6...

Page 151: ... R W R W R W R W R W bp Bit name Description 7 PRICKCNT07 Clock control for RTC function 0 disabled 1 enabled 6 PRICKCNT06 Clock control for Timer 6 and General time base timer 0 disabled 1 enabled 5 PRICKCNT05 Clock control for Timer 5 0 disabled 1 enabled 4 PRICKCNT04 Clock control for Timer 4 0 disabled 1 enabled 3 PRICKCNT03 Clock control for Timer 3 0 disabled 1 enabled 2 PRICKCNT02 Clock con...

Page 152: ...R W R W R W R W bp Bit name Description 7 PRICKCNT17 Clock control for DMA function 0 disabled 1 enabled 6 PRICKCNT16 Clock control for Serial 3 function 0 disabled 1 enabled 5 PRICKCNT15 Clock control for Serial 2 function 0 disabled 1 enabled 4 PRICKCNT14 Clock control for Serial 1 function 0 disabled 1 enabled 3 PRICKCNT13 Clock control for Serial 0 function 0 disabled 1 enabled 2 PRICKCNT12 Cl...

Page 153: ... R R W R W R W R W R W R W bp Bit name Description 7 6 Always read as 0 5 PRICKCNT25 Clock control for RTC time base timer function 0 disabled 1 enabled 4 PRICKCNT24 Clock control for Noise filter function Noise is removed by sampling 0 disabled 1 enabled 3 PRICKCNT23 Clock control for LVI function 0 disabled 1 enabled 2 PRICKCNT22 Clock control for 12 bit A D function 0 disabled 1 enabled 1 PRICK...

Page 154: ...apability of oscillation is not enough it can be changed by the rewriting enable register FBEWER 0x03D80 and the clock mode control register CLKMD 0x03D8C To change the current driving capability set the registers in operation with the internal low speed oscillation Figure 4 1 2 Change of the External Low speed Oscillation Capability Set the Rewriting Enable Register FBEWER 5A Set the Rewriting En...

Page 155: ...Figure 4 2 1 STOP mode STOP0 mode HALT mode NORMAL mode 1 1 1 1 1 2 2 2 2 CPU operation mode HALT0 mode HALT2 mode SLOW mode 1 Oscillation stabilization wait time is automatically inserted 2 When changing from the state that SCLK is stopped oscillation stabilization wait time is inserted 3 Ensure adequate time for oscillation stabilization by program HCLK stop SCLK CPU operation Reset IDLE mode HC...

Page 156: ...ching between HCLK and SCLK stable and synchronized the frequency of HCLK must be 2 5 times or more than that of SCLK Although HCLK oscillates in IDLE mode do not operate the peripheral circuits with HCLK Peripheral circuits must be enabled with HCLK after the CPU goes to NORMAL mode ...

Page 157: ...ode SYSCLK is generated from SCLK Figure 4 2 3 Transition Flow from SLOW to NORMAL through IDLE Transition to NORMAL mode Set the CPUM as described in Table 4 1 3 SLOW mode NORMAL mode Automatic high speed oscillation stabilization wait time by hardware NO Transition to OSC mode YES Transition to RC mode Start the external high speed oscillation HCLKCNT HOSCCNT 1 HCLKCNT HCLKSEL 0 Internal high sp...

Page 158: ...tion with the manufac turer of oscillator Clock Change from HOSCCLK to HRCCLK Figure 4 2 5 shows the clock change procedure from HOSCCLK to HRCCLK Figure 4 2 5 Clock Change Flow from HOSCCLK to HRCCLK External high speed oscillation stabilization wait time Start the external high speed oscillation HCLKCNT HOSCCNT 1 Switching the source oscillation of fosc HCLKCNT HCLKSEL 1 HCLKCNT HOSCCNT 1 NO YES...

Page 159: ...or external slow speed oscillation circuit or internal slow speed oscillation circuit Figure 4 2 6 Transition Flow from NORMAL Mode to SLOW Mode The oscillation stabilization wait time should be determined in consultation with the manufac turer of oscillator Transition to SLOW mode Set the CPUM as described in Table 4 1 3 The low speed oscillation stabilization wait time Start the low speed oscill...

Page 160: ...me should be determined in consultation with the manufac turer of oscillator Clock Change from SOSCCLK to SRCCLK Figure 4 2 8 shows the clock change procedure from SOSCCLK to SRCCLK Figure 4 2 8 Clock Change Flow from SOSCCLK to SRCCLK Start the external low speed oscillation SCLKCNT SOSCCNT 1 SCLKCNT SOSCCNT 1 NO YES SLOW mode SYSCLK SRCCLK SLOW mode SYSCLK SOSCCLK External low speed oscillation ...

Page 161: ...e up CPU from STANBY mode and set only the corresponding xICR IE to 1 Set the PSW MIE to 1 3 Set STANBY mode in the CPUM Figure 4 2 9 Transition to from STANDBY Mode NORMAL SLOW mode Disable all interrupts Enable interrupt which triggers return Watchdog timer HALT0 1 2 3 continue counting STOP stop counting Watchdog timer HALT0 1 2 3 continue counting STOP restart counting When returning from HALT...

Page 162: ...CMOD to 0 at the same time while the low speed oscillation is sta ble Transition procedure from SLOW mode to HALT1 HALT3 mode Set CPUM HALT to 1 If CPUM HALTMOD is 0 and 1 the mode changes to HALT1 and HALT3 respectively Transition procedure from NORMAL mode to HALT1 HALT3 mode Set CPUM HALT to 1 CPUM OSCMOD to 0 and CPUM CLKSEL to 0 at the same time while the low speed oscillation is stable If CP...

Page 163: ...rger than the value of PSW IM1 0 before transition to STANDBY mode it is impossible to return to CPU operating mode by a maskable interrupt Transition to HALT3 mode Set the CPUM as described in Table 4 1 3 CPUM XIMOD 1 NO YES HALT3 mode NORMAL SLOW mode The low speed oscillation stabilization wait time Start the low speed oscillation CPUM XIMOD 1 When SCLKCNT SOSCCNT 1 SOSCCLK starts When SCLKCNT ...

Page 164: ...CPUM STOP to 1 Transition procedure from SLOW mode to STOP1 mode Set CPUM STOP to 1 Transition procedure from NORMAL mode to STOP1 mode Set CPUM STOP to 1 CPUM OSCMOD to 0 and CPUM CLKSEL to 0 at the same time while the low speed oscillation is stable Transition procedure from SLOW mode to STOP0 mode Set CPUM STOP to 1 CPUM OSCMOD to 1 and CPUM CLKSEL to 1 at the same time Figure 4 2 12 Transition...

Page 165: ...curs before the transition to STANDBY mode CPU can return to CPU operating mode by a maskable interrupt for wakeup since the interrupt is detected after the transi tion to STANDBY mode However the interrupt processing is not executed because CPU just returns to CPU operating mode in this func tion To execute the interrupt processing it is necessary to set PSW MIE to 1 after returning to CPU operat...

Page 166: ...ernal RAM NORMAL SLOW mode Disable maskable interrupts Enable interrupt which triggers return Enable maskable interrupts HALT STOP mode NORMAL SLOW mode Set HALT STOP mode Interrupt service routine Set the xICR IE of the return factor to 1 Set the PSW MIE to 0 and set all interrupt enable bits xICR IE to 0 Watchdog timer HALT0 1 2 3 continue counting STOP stop counting Return factor interrupt occu...

Page 167: ... interrupt request flag xICR IR 0 Disable writing of the interrupt request flag MEMCTR IRWE 0 Execute following program NORMAL SLOW mode Disable maskable interrupts Enable interrupt which triggers return Enable maskable interrupts HALT STOP mode NORMAL SLOW mode Set HALT STOP mode Set the xICR IE of the return factor to 1 Set the PSW MIE to 0 and set all interrupt enable bits xICR IE to 0 Watchdog...

Page 168: ...1 Relation of Output Voltage VDD18 to Operating Power Supply Voltage Frequency and Mode 4 3 2 Register List Table 4 3 2 shows a list of power supply control registers Table 4 3 2 Power Supply Control Registers R W Readable Writable Enable Setting is prohibited VDD30 Operating power supply range V Maximum operating frequency VDD18 Output voltage V Operating mode NORMAL SLOW HALT0 2 STOP0 HALT1 3 ST...

Page 169: ...er can be update only in SLOW mode The voltage of VDD18 can be changed to match the following conditions 1 1 V to 1 8 V or 1 8 V to 1 1 V 1 1 V to 1 3 V or 1 3 V to 1 1 V The voltage of VDD18 must not be changed in the following conditions 1 3 V to 1 8 V or 1 8 V to 1 3 V bp 7 6 5 4 3 2 1 0 Bit name Reserved Reserved Reserved Reserved Reserved Reserved VDDLV1 VDDLV0 Initial value 1 0 0 0 0 0 0 0 A...

Page 170: ...W R W R W bp Bit name Description 7 Reserved Always set to 0 6 Reserved When transition of VDD18 set to 1 after the microcomputer starts up 5 Always read as 0 4 DEEPMOD VDD18 setting when the transition from NORMAL mode to HALT2 STOP0 mode 0 Voltage transition disabled 1 Change to 1 1 V Voltage returns to the same level as it was before the transition at return CPU starts up again after the time s...

Page 171: ... halted while the voltage is stepped down during ii and iv shown in the Figure 4 3 1 it does not affect the operation Figure 4 3 1 Voltage Transition of VDD18 by Program The setting example to change VDD18 from 1 1 V to 1 8 V at iii in Figure 4 3 1 is shown below CPU outage in voltage transition 32 fSCLK fSCLK 32 768 kHz 977 µs Be sure to execute the setting in SLOW mode Step Setting Register name...

Page 172: ... to 1 Figure 4 3 2 Voltage Transition of VDD18 by Mode Transition The setting example of the transition to Deep STANDBY mode in Figure 4 3 2 is shown below Step Setting Register name Description 1 Set Deep STANDBY mode PWCTR1 Set DEEPMOD to 1 2 Set output voltage VDD18 PWCTR0 Set VDDLV1 0 to 10 3 Set the oscillation stabilization wait and interrupt DLYCTR XXXICR For the oscillation stabilization w...

Page 173: ...DD18 voltage _ SYSCLK _ Oscillating clock except SYSCLK _ Special mode SYSCLK is described in NORMAL SLOW IDLE HALT0 or HALT1 mode Oscillating clock except SYSCLK or Special mode that corresponded to each condition is described For example NORMAL_18_HCLK_SCLK NORMAL mode VDD18 1 8 V SYSCLK HCLK HOSC HRC SCLK SOSC SRC Oscillating HALT2_11_SCLK_DEEP HALT2 mode VDD18 1 1 V SYSCLK Stop SCLK SOSC SRC O...

Page 174: ...CLK M 3 M 3 V M 3 M 3 M M M M M M 4 SLOW_11_SCLK V V M M M HALT0_18_HCLK_SCLK M HALT0_18_HCLK M HALT0_13_HRC_SCLK M HALT0_13_HRC M HALT1_18_SCLK M HALT1_13_SCLK M HALT1_11_SCLK M HALT2_18_SCLK M 3 HALT2_13_SCLK M 3 HALT2_11_SCLK_DEEP M V 5 M V 6 HALT3_18_SCLK M HALT3_13_SCLK M HALT3_11_SCLK M STOP0_18 M 3 M 3 STOP0_13 M 3 M 3 STOP0_11_DEEP M V 5 M V 6 STOP1_18 M 2 STOP1_13 M 2 STOP1_11 M 2 IDLE_18...

Page 175: ...V Chapter 5 Watchdog Timer WDT 5 ...

Page 176: ... when WDT is active WDT Counter is initialized when the LSI is reset or is in STOP mode Table 5 1 1 Relationship between CPU mode and WDT operation When the WDIRQ is generated the LSI can be in unexpected state Therefore appropriate measures to make the LSI operate normally should be taken CPU mode WDT Counter operation NORMAL IDLE SLOW HALT Continue to count Count operation doesn t stop even duri...

Page 177: ... when the LSI is reset bp 7 6 5 4 3 2 1 0 Bit name WDCKSEL WDTS2 0 WDEN At reset 0 0 0 0 0 0 0 0 Access R W R R R R W R W R W R W bp Bit name Description 7 WDCKSEL Select watchdog time clock source 0 SRCCLK 1 SOSCCLK 6 4 Always read as 0 3 1 WDTS2 0 Watchdog error detect period setup 000 27 1 fWDTCLK 001 28 1 fWDTCLK 010 29 1 fWDTCLK 011 211 1 fWDTCLK 100 212 1 fWDTCLK 101 214 1 fWDTCLK 110 216 1 ...

Page 178: ...lly to avoid WDT overflow WDT Counter is cleared by writing something on the WDCTR WDT generates WDIRQ when WDT Counter is not cleared during the error detect period and overflows WDT counter should be cleared with BSET instruction for example BSET WDCTR 0 to avoid changing the error detection time etc unintentionally ...

Page 179: ...etup Procedure Register Description 1 Set the error detection period WDCTR Set the WDCKSEL to 0 Set the WDTS2 0 to 111 2 Activate WDT WDCTR Set the WDEN to 1 Step Setup Procedure Register Description 1 Clear WDT Counter WDCTR Clear WDT counter before it overflows Step Setup Procedure Register Description 1 Handling interrupt NMICR WDIRQ is generated when WDT Counter overflows Check that NMICR IRQN...

Page 180: ...Chapter 5 Watchdog Timer WDT V 6 Operation ...

Page 181: ...VI Chapter 6 Power Supply Voltage Detection 6 ...

Page 182: ...r supply voltage detection function is OFF LVION 0 1 Though power supply voltage at falling falls below the detection voltage VLVI the interrupt request is not generated and the LVIOUT bit is not cleared 2 Though power supply voltage at rising exceeds the detection voltage VLVI the interrupt request is not generated and the LVIOUT bit is not cleared Power supply voltage detection function is ON LV...

Page 183: ...sters Table 6 2 1 shows the PSVD related registers Table 6 2 1 Power Supply Voltage Detection Control Registers Symbol Address R W Register name Page LVICTR0 0x03F66 R W PSVD control register 0 VI 4 LVICTR1 0x03F67 R W PSVD control register 1 VI 5 LVICTR2 0x03F68 R W PSVD control register 2 VI 6 ...

Page 184: ... 0 0 0 0 0 0 0 0 Access R W R R R W R W R W R W R W bp Bite name Description 7 Reserved Must be set to 0 6 5 Always read as 0 4 0 LV4 0 The level of VLVI 00000 1 10 V 00001 1 15 V 00010 1 20 V 00011 1 25 V 00100 1 30 V 00101 1 35 V 00110 1 40 V 00111 1 50 V 01000 1 60 V 01001 1 70 V 01010 1 80 V 01011 1 90 V 01100 2 00 V 01101 2 10 V 01110 2 20 V 01111 2 30 V 10000 2 40 V 10001 2 50 V 10010 2 60 V...

Page 185: ...ERI1EN PERI1EN0 more than 1 5 ms is required since the LVION is set to 1 To read the LVICTR1 LVIOU more than 1 5 ms is required since the LVION is set to 1 bp 7 6 5 4 3 2 1 0 Bit name LVIOUT LVION At reset 0 0 0 0 0 0 0 0 Access R R R R R R R W R W bp Bite name Description 7 2 Always read as 0 1 LVIOUT VDD30 monitor bit 0 VDD30 VLVI 1 VDD30 VLVI 0 LVION PSVD enable control 0 Disabled 1 Enabled ...

Page 186: ...nd the sampling frequency of it bp 7 6 5 4 3 2 1 0 Bit name LVINFSCK2 0 LVINFEN At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bite name Description 7 4 Always read as 0 3 1 LVINFSCK2 0 Noise sampling frequency 000 fHCLK 001 fHCLK 25 010 fHCLK 26 011 fHCLK 27 100 fHCLK 28 101 fHCLK 29 110 fHCLK 210 111 fSCLK 0 LVINFEN Noise filter enable control 0 Disabled 1 Enabled ...

Page 187: ...e the power supply voltage detection function 4 Wait for power supply voltage detection function activation wait 1 5 ms 4 Wait for the power supply voltage function activation time 1 5 ms or more 5 Clear the interrupt request bit PERI1DT 0x03FDF 5 Clear the interrupt request bits by reading PERI1DT and writing the read value to PERI1DT Refer to 3 1 4 Group Interrupt Control Register Setup 6 Set th...

Page 188: ... addresses saved to stack in interrupt processing If it is considered that the operation as above occurred rewrite the value of stack address or saved data to prevent the standby transition program execution 10 When the LVIOUT bit is 0 operating mode transits to STOP mode CPUM 0x03F00 bp3 STOP 1 10 When the monitored LVIOUT bit is 0 the operating mode transits to STOP mode 11 Return from STOP mode...

Page 189: ...VII Chapter 7 I O Port 7 ...

Page 190: ...rol registers Table 7 1 1 I O port status at reset single chip mode Port I O mode Pull up resistor I O port Special function Port 0 Input mode No pull up resistor I O port Port 1 Input mode No pull up resistor I O port Port 2 Input mode P27 Pull up resistor Others No pull up resistor I O port Port 3 Input mode No pull up resistor I O port Port 4 Input mode No pull up resistor I O port Port 5 Input...

Page 191: ...ty selection register VII 22 P3OUT 0x03F13 R W Port 3 output register VII 6 P3IN 0x03F23 R Port 3 input register VII 9 P3DIR 0x03F33 R W Port 3 direction control register VII 13 P3PLUP 0x03F43 R W Port 3 pull up resistor control register VII 16 P3ODC 0x03F53 R W Port 3 N ch open drain control register VII 19 P3NLC 0x03EC2 R W Port 3 N ch current capacity selection register VII 22 P4OUT 0x03F14 R W...

Page 192: ...t pin selection register VII 26 TMIOEN1 0x03F2E R W 16 bit timer output control register VII 27 TMIOSEL1 0x03F2F R W 16 bit timer input output pin selection register VII 28 CLKOUT 0x03F3E R W Clock output control register VII 29 IRQIEN 0x03F4C R W External interrupt input control register III 35 IRQISEL0 0x03F4D R W External interrupt input pin selection register 0 III 36 IRQISEL1 0x03F3F R W Exte...

Page 193: ...Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P0OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P1OUT7 0 At reset X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P1OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P2OUT7 0 At reset X X X X X X X X Ac...

Page 194: ...tion 7 0 P3OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P4OUT7 0 At reset X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P4OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P5OUT7 0 At reset X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Descripti...

Page 195: ...P6OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P7OUT7 0 At reset X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P7OUT7 0 Output data 0 Output Low VSS level 1 Output High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P8OUT5 0 At reset 0 0 X X X X X X Access R R R W R W R W R W R W R W bp Bit name Description 7 6 Always...

Page 196: ...3F20 Port 1 Input Register P1IN 0x03F21 bp 7 6 5 4 3 2 1 0 Bit name P0IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P0IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P1IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P1IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level ...

Page 197: ...t name Description 7 0 P2IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P3IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P3IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P4IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P4IN7 0 Input data 0 ...

Page 198: ...name Description 7 0 P5IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P6IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P6IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level bp 7 6 5 4 3 2 1 0 Bit name P7IN7 0 At reset X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 P7IN7 0 Input data 0 In...

Page 199: ...II 11 Port 8 Input Register P8IN 0x03F28 bp 7 6 5 4 3 2 1 0 Bit name P8IN5 0 At reset 0 0 X X X X X X Access R R R R R R R R bp Bit name Description 7 6 Always read as 0 5 0 P8IN7 0 Input data 0 Input Low VSS level 1 Input High VDD30 level ...

Page 200: ... name P0DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P0DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P1DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P1DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P2DIR6 0 At reset 0 0 0 ...

Page 201: ... W R W R W R W R W bp Bit name Description 7 0 P3DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P4DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P4DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P5DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name...

Page 202: ...W R W R W bp Bit name Description 7 0 P6DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P7DIR7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P7DIR7 0 I O mode selection 0 Intput mode 1 Output mode bp 7 6 5 4 3 2 1 0 Bit name P8DIR5 0 At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W bp Bit name Description ...

Page 203: ...it name P0PLU7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P0PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P1PLU7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P1PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P2PLU6 0 At reset 0 0 ...

Page 204: ... W R W R W R W R W R W R W R W bp Bit name Description 7 0 P3PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P4PLU7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P4PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P5PLU7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W...

Page 205: ...W R W R W R W R W R W bp Bit name Description 7 0 P6PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P7PLU7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P7PLU7 0 Pull up resistor selection 0 Not added 1 Added bp 7 6 5 4 3 2 1 0 Bit name P8PLU5 0 At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W bp Bit name ...

Page 206: ...0 0 0 0 0 0 0 Access R W R R W R W R R R R bp Bit name Description 7 P0ODC7 N ch open drain output selection 0 Push pull output 1 N ch open drain output 6 Always read as 0 5 4 P0ODC5 4 N ch open drain output selection 0 Push pull output 1 N ch open drain output 3 0 Always read as 0 bp 7 6 5 4 3 2 1 0 Bit name P1ODC5 At reset 0 0 0 0 0 0 0 0 Access R R R W R R R R R bp Bit name Description 7 6 Alwa...

Page 207: ...ion 7 6 Always read as 0 5 3 P2ODC5 3 N ch open drain output selection 0 Push pull output 1 N ch open drain output 2 0 Always read as 0 bp 7 6 5 4 3 2 1 0 Bit name P3ODC7 6 P3ODC2 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R R R R W R W R W bp Bit name Description 7 6 P3ODC7 6 N ch open drain output selection 0 Push pull output 1 N ch open drain output 5 3 Always read as 0 2 0 P3ODC2 0 N ch open dr...

Page 208: ... drain output 5 Always read as 0 4 2 P4ODC4 2 N ch open drain output selection 0 Push pull output 1 N ch open drain output 1 Always read as 0 0 P4ODC0 N ch open drain output selection 0 Push pull output 1 N ch open drain output bp 7 6 5 4 3 2 1 0 Bit name P5ODC4 2 P5ODC0 At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R W R R W bp Bit name Description 7 5 Always read as 0 4 2 P5ODC4 2 N ch open drai...

Page 209: ...drain Control Register P6ODC 0x03F56 bp 7 6 5 4 3 2 1 0 Bit name P6ODC7 5 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R R R R R bp Bit name Description 7 5 P6ODC7 5 N ch open drain output selection 0 Push pull output 1 N ch open drain output 4 0 Always read as 0 ...

Page 210: ... R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P0NLC7 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current capacity 8mA bp 7 6 5 4 3 2 1 0 Bit name P2NLC6 0 At reset 0 0 0 0 0 0 0 0 Access R R W R W R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 0 P2NLC6 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current capaci...

Page 211: ...t 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P4NLC7 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current capacity 8mA bp 7 6 5 4 3 2 1 0 Bit name P5NLC7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P5NLC7 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current...

Page 212: ...t 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P6NLC7 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current capacity 8mA bp 7 6 5 4 3 2 1 0 Bit name P7NLC7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 P7NLC7 0 N ch current capacity selection 0 normal current capacity 2mA 1 Large current...

Page 213: ...scription 7 6 Always read as 0 5 TM5OEN Select the pin function GIO or Timer 5 output 0 GIO 1 Timer 5 output TM5IOA TM5IOB 4 TM4OEN Select the pin function GIO or Timer 4 output 0 GIO 1 Timer 4 output TM4IOA TM4IOB 3 TM3OEN Select the pin function GIO or Timer 3 output 0 GIO 1 Timer 3 output TM3IOA TM3IOB 2 TM2OEN Select the pin function GIO or Timer 2 output 0 GIO 1 Timer 2 output TM2IOA TM2IOB 1...

Page 214: ...0 0 0 Access R R R W R W R W R W R W R W bp Bit name Description 7 6 Always read as 0 5 TM5IOSEL Select the pin of Timer 5 TM5IOA or TM5IOB 0 TM5IOA P21 1 TM5IOB P73 4 TM4IOSEL Select the pin of Timer 4 TM4IOA or TM4IOB 0 TM4IOA P34 1 TM4IOB P01 3 TM3IOSEL Select the pin of Timer 3 TM3IOA or TM3IOB 0 TM3IOA P56 1 TM3IOB P72 2 TM2IOSEL Select the pin of Timer 2 TM2IOA or TM2IOB 0 TM2IOA P05 1 TM2IO...

Page 215: ...p 7 6 5 4 3 2 1 0 Bit name TM9OEN TM8OEN TM7OEN At reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W bp Bit name Description 7 3 Always read as 0 2 TM9OEN Select the pin function GIO or Timer 9 output 0 GIO 1 Timer 9 output TM9IOA TM9IOB TM9IOC 1 TM8OEN Select the pin function GIO or Timer 8 output 0 GIO 1 Timer 8 output TM8IOA TM8IOB TM8IOC 0 TM7OEN Select the pin function GIO or Timer 7 output ...

Page 216: ...M9IOSEL1 0 TM8IOSEL1 0 TM7IOSEL1 0 At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W bp Bit name Description 7 6 Always read as 0 5 4 TM9IOSEL 1 0 Select the pin of Timer 9 from TM9IOA to TM9IOC 00 TM9IOA P07 01 TM9IOB P20 10 TM9IOC P00 11 Prohibited 3 2 TM8IOSEL 1 0 Select the pin of Timer 8 from TM8IOA to TM8IOC 00 TM8IOA P57 01 TM8IOB P06 10 TM8IOC P02 11 Prohibited 1 0 TM7IOSEL 1 0 S...

Page 217: ... Register CLKOUT 0x03F3E bp 7 6 5 4 3 2 1 0 Bit name CLKOCNT1 0 CLKO SEL CLKOEN At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 Always read as 0 3 2 CLKOCNT 1 0 Select output clock 00 SCLK 01 HCLK 10 SYSCLK 11 Time base timer output clock for RTC 1 CLKOSEL Select the output pin of clock output function 0 CLKOUTA P05 1 CLKOUTB P57 0 CLKOEN Select the pin function...

Page 218: ...register selects the pin function General IO GIO or A D input Analog Input Control Register 0 Port 1 ANEN0 0x03F5C bp 7 6 5 4 3 2 1 0 Bit name ANEN07 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 ANEN07 0 Select the pin function GIO or A D input 0 GIO 1 A D input ...

Page 219: ...0 0 0 0 0 0 Access R R R W R W R W R W R W R W bp Bit name Description 7 6 Always read as 0 5 ANEN15 Select the pin function GIO or Analog input 0 GIO P85 1 VLC2 4 ANEN14 Select the pin function GIO or Analog input 0 GIO P84 1 VLC3 3 ANEN13 Select the pin function GIO or Analog input 0 GIO P83 1 C2 2 ANEN12 Select the pin function GIO or Analog input 0 GIO P82 1 C1 1 ANEN11 Select the pin function...

Page 220: ...control Register BUZCNT 0x03F5F bp 7 6 5 4 3 2 1 0 Bit name NBUZEN BUZEN NBUZSEL BUZSEL At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 Always read as 0 3 NBUZEN Select the pin function GIO or NBUZ output 0 GIO 1 NBUZ output NBUZA NBUZB 2 BUZEN Select the pin function GIO or BUZ output 0 GIO 1 BUZ output BUZA BUZB 1 NBUZSEL Select the output pin of NBUZ output f...

Page 221: ...N PnDIR PnPLU PnODC and PnNLC registers Each port also has a special function the detail of which is described after 7 4 Port 0 The assignment and selection of LCD control pins SEGn and COMn differ in each product For details refer to Table 1 2 3 Functions of LCD Control and 17 2 2 LCD Port Control Reg isters MN101LR05D is described in this section ...

Page 222: ...M4IOB P02 TM2IOB TM8IOC BUZB P03 TM0IOB TM7IOC NBUZB P04 SBO3A SDA3A TM7IOA P05 SBT3A SCL3A TM0IOA TM2IOA CLKOUTA P06 SBI3A TM8IOB P07 SBCS3A TM9IOA Setup Function Register TMIOEN1 TM9MD1 TMIOSEL1 Bit name TM9OEN TM9CK1 0 TM9IOSEL1 0 1 Other than 10 10 TM9IO output 0 10 10 TM9IO input Other than 10 P00 Setup Function Register TMIOEN0 TM4MD TMIOSEL0 Bit name TM4OEN TM4CK1 0 TM4IOSEL 1 Other than 11...

Page 223: ...n 11 1 Other than 10 10 0 TM8IO output 0 10 10 0 TM8IO input Other than 10 1 1 BUZB 0 P02 Setup Function Register TMIOEN0 TM0MD TMIOSEL0 TMIOEN1 TM7MD1 TMIOSEL1 BUZCNT Bit name TM0OEN TM0CK1 0 TM0IOSEL TM7OEN TM7CK1 0 TM7IOSEL 1 0 NBUZEN NBUZSEL 1 Other than 11 1 0 Other than 10 0 TM0IO output 0 11 1 0 Other than 10 0 TM0IO input Other than 11 1 Other than 10 10 0 TM7IO output 0 10 10 0 TM7IO inpu...

Page 224: ...LKOSEL 1 1 0 Other than 11 0 Other than 11 0 0 SBT3A SCL3A 0 Other than 11 1 Other than 11 0 0 0 TM0IO output 11 0 Other than 11 0 0 0 TM0IO input Other than 11 Other than 11 1 0 0 TM2IO output 11 0 0 0 TM2IO input Other than 11 1 0 CLKOUTA 0 P05 Setup Function Register SC3MD1 SC23SEL TMIOEN1 TM8MD1 TMIOSEL1 Bit name SC3SBIS SC3IOM SC3SEL0 TM8OEN TM8CK1 0 TM8IOSEL 1 0 1 0 0 0 Other than 10 SBI3A 0...

Page 225: ...N0 IRQ0A KEY0A P11 AN1 IRQ1A KEY1A P12 AN2 IRQ4C KEY2A P13 AN3 IRQ5C KEY3A P14 AN4 IRQ4A KEY4A P15 AN5 IRQ5A KEY5A P16 AN6 IRQ6A KEY6A P17 AN7 KEY7A Setup Function Register ANEN0 IRQIEN IRQISEL0 KEYIEN KEYSEL Bit name ANEN00 IRQI0EN IRQ0SEL KEYI0EN KEY0SEL 1 AN0 0 1 0 0 IRQ0A 0 1 0 KEY0A 0 P10 Setup Function Register ANEN0 IRQIEN IRQISEL0 KEYIEN KEYSEL Bit name ANEN01 IRQI1EN IRQ1SEL KEYI1EN KEY1S...

Page 226: ...Q4C 0 1 0 KEY2A 0 P12 Setup Function Register ANEN0 IRQIEN IRQISEL1 KEYIEN KEYSEL Bit name ANEN03 IRQI5EN IRQ5CSEL KEYI3EN KEY3SEL 1 AN3 0 1 1 0 IRQ5C 0 1 0 KEY3A 0 P13 Setup Function Register ANEN0 IRQIEN IRQISEL0 IRQISEL1 KEYIEN KEYSEL Bit name ANEN04 IRQI4EN IRQ4SEL IRQ4CSEL KEYI4EN KEY4SEL 1 AN4 0 1 0 0 0 IRQ4A 0 1 0 KEY4A 0 P14 Setup Function Register ANEN0 IRQIEN IRQISEL0 IRQISEL1 KEYIEN KEY...

Page 227: ... 7 5 9 P17 Function Selection Setup Function Register ANEN0 IRQIEN IRQISEL0 KEYIEN KEYSEL Bit name ANEN06 IRQI6EN IRQ6SEL KEYI6EN KEY6SEL 1 AN6 0 1 0 0 IRQ6A 0 1 0 KEY6A 0 P16 Setup Function Register ANEN0 KEYIEN KEYSEL Bit name ANEN07 KEYI7EN KEY7SEL 1 AN7 0 1 0 KEY7A 0 P17 ...

Page 228: ...0 Function Selection pin Special function P20 SEG42 TM1IOB TM9IOB P21 SEG41 TM5IOA P22 SEG40 SBI2B P23 SEG39 SBO2B SDA2B P24 SEG38 SBT2B SCL2B P25 SEG37 SBCS2B P26 SEG36 SBI1A RXD1A P27 NRST Setup Function Register LCCTR5 TMIOEN0 TM1MD TMIOSEL0 TMIOEN1 TM9MD1 TMIOSEL1 Bit name SEGSL42 TM1OEN TM1CK1 0 TM1IOSEL TM9OEN TM9CK1 0 TM9IOSEL 1 0 1 SEG42 0 1 Other than 11 1 0 Other than 10 TM1IO output 0 1...

Page 229: ...s set the P2DIR P2DIR4 to 1 Setup Function Register LCCTR5 TMIOEN0 TM5MD TMIOSEL5 Bit name SEGSL41 TM5OEN TM5CK1 0 TM5IOSEL 1 SEG41 0 1 Other than 11 0 TM5IO output 0 11 0 TM5IO input Other than 11 P21 Setup Function Register LCCTR5 SC2MD1 SC23SEL Bit name SEGSL40 SC2SBIS SC2IOM SC2SEL0 1 SEG40 0 1 0 1 SBI2B 0 0 P22 Setup Function Register LCCTR5 SC2MD1 SC23SEL Bit name SEGSL39 SC2SBOS SC2SBIS SC2...

Page 230: ...elect signal set the P2DIR P2DIR5 to 1 Table 7 6 8 P26 Function Selection Setup Function Register LCCTR5 SC2MD2 SC23SEL Bit name SEGSL37 SC2SBCSEN SC2SEL3 1 SEG37 0 1 1 SBCS2B 0 P25 Setup Function Register LCCTR5 SC1MD1 SC01SEL Bit name SEGSL36 SC1SBIS SC1IOM SC1SEL0 1 SEG36 0 1 0 0 SBI1A RXD1A 0 0 P26 ...

Page 231: ...Setup of Port 3 Table 7 7 2 P30 Function Selection 1 When serial data is output set the P3DIR P3DIR0 to 1 2 When serial data is input and output set the bit to 1 pin Special function P30 SEG35 SBO1A TXD1A P31 SEG34 SBT1A P32 SEG33 SBCS1A P33 SEG32 BUZA P34 SEG31 TM4IOA TM7IOB NBUZA P35 SEG30 SBI0B RXD0B P36 SEG29 SBO0B TXD0B P37 SEG28 SBT0B Setup Function Register LCCTR4 SC1MD1 SC01SEL Bit name SE...

Page 232: ...SL34 SC1SBTS SC1SEL2 1 SEG34 0 1 1 0 SBT1A 0 P31 Setup Function Register LCCTR4 SC1MD3 SC01SEL Bit name SEGSL33 SC1SBCSEN SC1SEL3 1 SEG33 0 1 1 0 SBCS1A 0 P32 Setup Function Register LCCTR4 BUZCNT Bit name SEGSL32 BUZEN BUZSEL 1 SEG32 0 1 0 BUZA 0 P33 Setup Function Register LCCTR4 TMIOEN0 TM4MD TMIOSEL0 TMIOEN1 TM7MD1 TMIOSEL1 BUZCNT Bit name SEGSL31 TM4OEN TM4CK 1 0 TM4IOSEL TM7OEN TM7CK 1 0 TM7...

Page 233: ...n the LSI is the master of Clock synchronous communication set the P3DIR P3DIR7 to 1 Setup Function Register LCCTR4 SC0MD1 SC01SEL Bit name SEGSL30 SC0SBIS SC0IOM SC0SEL0 1 SEG30 0 1 0 1 SBI0B RXD0B 0 0 P35 Setup Function Register LCCTR4 SC0MD1 SC01SEL Bit name SEGSL29 SC0SBOS SC0SBIS SC0IOM SC0SEL1 1 SEG29 0 1 1 2 2 1 SBO0B TXD0B 0 1 1 1 0 0 P36 Setup Function Register LCCTR4 SC0MD1 SC01SEL Bit n...

Page 234: ...ion Selection 1 When the LSI outputs the chip select signal set the P4DIR P4DIR0 to 1 Table 7 8 3 P41 Function Selection pin Special function P40 SEG27 SBCS0B P41 SEG26 SBI2A P42 SEG25 SBO2A SDA2A P43 SEG24 SBT2A SCL2A P44 SEG23 SBCS2A P45 SEG22 SBI1B RXD1B P46 SEG21 SBO1B TXD1B P47 SEG20 SBT1B Setup Function Register LCCTR3 SC0MD3 SC01SEL Bit name SEGSL27 SC0SBCSEN SC0SEL3 1 SEG27 0 1 1 1 SBCS0B ...

Page 235: ...I outputs the chip select signal set the P4DIR P4DIR4 to 1 Table 7 8 7 P45 Function Selection Setup Function Register LCCTR3 SC2MD1 SC23SEL Bit name SEGSL25 SC2SBOS SC2SBIS SC2IOM SC2SEL1 1 SEG25 0 1 1 2 2 0 SBO2A SDA2A 0 1 1 0 0 0 P42 Setup Function Register LCCTR3 SC2MD1 SC23SEL Bit name SEGSL24 SC2SBTS SC2SEL2 1 SEG24 0 1 1 0 SBT2A SCL2A 0 P43 Setup Function Register LCCTR3 SC2MD2 SC23SEL Bit n...

Page 236: ...o 1 Table 7 8 9 P47 Function Selection 1 When the LSI is the master of Clock synchronous communication set the P4DIR P4DIR7 to 1 Setup Function Register LCCTR3 SC1MD1 SC01SEL Bit name SEGSL21 SC1SBOS SC1SBIS SC1IOM SC1SEL1 1 SEG21 0 1 1 2 2 1 SBO1B TXD1B 0 1 1 1 0 0 P46 Setup Function Register LCCTR3 SC1MD1 SC01SEL Bit name SEGSL20 SC1SBTS SC1SEL2 1 SEG20 0 1 1 1 SBT1B 0 P47 ...

Page 237: ...on 1 When the LSI outputs the chip select signal set the P5DIR P5DIR0 to 1 Table 7 9 3 P51 Function Selection pin Special function P50 SEG19 SBCS1B P51 SEG18 SBI3B P52 SEG17 SBO3B SDA3B P53 SEG16 SBT3B SCL3B P54 SEG15 KEY0B SBCS3B P55 SEG14 KEY1B TM1IOA P56 SEG13 KEY2B TM3IOA P57 SEG12 KEY3B TM8IOA CLKOUTB Setup Function Register LCCTR2 SC1MD3 SC01SEL Bit name SEGSL19 SC1SBCSEN SC1SEL3 1 SEG19 0 1...

Page 238: ...on Setup Function Register LCCTR2 SC3MD1 SC23SEL Bit name SEGSL17 SC3SBOS SC3SBIS SC3IOM SC3SEL1 1 SEG17 0 1 1 2 2 1 SBO3B SDA3B 0 1 1 1 0 0 P52 Setup Function Register LCCTR2 SC3MD1 SC23SEL Bit name SEGSL16 SC3SBTS SC3SEL2 1 SEG16 0 1 1 1 SBT3B SCL3B 0 P53 Setup Function Register LCCTR2 KEYIEN KEYSEL SC3MD2 SC23SEL Bit name SEGSL15 KEYI0EN KEY0SEL SC3SBCS EN SC3SEL3 1 SEG15 0 1 1 0 KEY0B 0 1 1 1 ...

Page 239: ...EN TM3CK1 0 TM3IOSEL 1 SEG13 0 1 1 0 Other than 11 KEY2B 0 1 Other than 11 0 TM3IO output 0 11 0 TM3IO input Other than 11 P56 Setup Function Register LCCTR2 KEYIEN KEYSEL TMIOEN1 TM8MD1 TMIOSEL1 CLKOUT Bit name SEGSL12 KEYI3EN KEY3SEL TM8OEN TM8CK1 0 TM8IOSEL 1 0 CLKOEN CLKOSEL 1 0 SEG12 0 1 1 0 Other than 10 0 KEY3B 0 1 Other than 10 00 0 TM8IO output 0 10 00 0 TM8IO input Other than 10 1 1 CLKO...

Page 240: ...0 1 Setup of Port 6 Table 7 10 2 P60 Function Selection Table 7 10 3 P61 Function Selection pin Special function P60 SEG11 IRQ0B P61 SEG10 IRQ1B P62 SEG9 IRQ2B P63 SEG8 IRQ3B P64 SEG7 KEY4B SBI0A RXD0A P65 SEG6 KEY5B SBO0A TXD0A P66 SEG5 KEY6B SBT0A P67 SEG4 KEY7B SBCS0A Setup Function Register LCCTR1 IRQIEN IRQISEL0 Bit name SEGSL11 IRQI0EN IRQ0SEL 1 SEG11 0 1 1 IRQ0B 0 P60 Setup Function Registe...

Page 241: ...N IRQISEL0 Bit name SEGSL9 IRQI2EN IRQ2SEL 1 SEG9 0 1 1 IRQ2B 0 P62 Setup Function Register LCCTR1 IRQIEN IRQISEL0 Bit name SEGSL8 IRQI3EN IRQ3SEL 1 SEG8 0 1 1 IRQ3B 0 P63 Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD1 SC01SEL Bit name SEGSL7 KEYI4EN KEY4SEL SC0SBIS SC0IOM SC0SEL0 1 SEG7 0 1 1 0 0 KEY4B 0 1 0 0 SBI0A RXD0A 0 0 P64 Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD1 SC01SEL Bi...

Page 242: ...n Selection 1 When the LSI outputs the chip select signal set the P6DIR P6DIR7 to 1 Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD1 SC01SEL Bit name SEGSL5 KEYI6EN KEY6SEL SC0SBTS SC0SEL2 1 SEG5 0 1 1 0 KEY6B 0 1 1 0 SBT0A 0 P64 Setup Function Register LCCTR1 KEYIEN KEYSEL SC0MD3 SC01SEL Bit name SEGSL4 KEYI7EN KEY7SEL SC0SBCSEN SC0SEL3 1 SEG4 0 1 1 0 KEY7B 0 1 1 0 SBCS0A 0 P67 ...

Page 243: ...11 1 Setup of Port 7 Table 7 11 2 P70 Function Selection Table 7 11 3 P71 Function Selection pin Special function P70 COM7 SEG3 IRQ6B P71 COM6 SEG2 IRQ5B P72 COM5 SEG1 IRQ4B TM3IOB P73 COM4 SEG0 TM5IOB P74 COM3 P75 COM2 P76 COM1 P77 COM0 Setup Function Register LCCTR0 LCDSEL IRQIEN IRQISEL0 Bit name SEGSL3 COMSL7 IRQI6EN IRQ6SEL 1 1 COM7 1 0 SEG3 0 1 1 IRQ6B 0 P70 Setup Function Register LCCTR0 LC...

Page 244: ...L5 IRQI4EN IRQ4SEL TM3OEN TM3CK1 0 TM3IOSEL 1 1 COM5 1 0 SEG1 0 1 1 0 Other than 11 IRQ4B 0 1 Other than 11 1 TM3IO output 0 11 1 TM3IO input Other than 11 P72 Setup Function Register LCCTR0 LCDSEL TMIOEN0 TM5MD TMIOSEL0 Bit name SEGSL0 COMSL4 TM5OEN TM5CK1 0 TM5IOSEL 1 1 COM4 1 0 SEG0 0 1 Other than 11 1 TM5IO output 0 11 1 TM5IO input Other than 11 P73 Setup Function Register LCCTR0 Bit name COM...

Page 245: ... O Port Port 7 VII 57 Table 7 11 8 P76 Function Selection Table 7 11 9 P77 Function Selection Setup Function Register LCCTR0 Bit name COMSL1 1 COM1 0 P76 Setup Function Register LCCTR0 Bit name COMSL0 1 COM0 0 P77 ...

Page 246: ...s shown below Table 7 12 2 P80 Function Selection Table 7 12 3 P81 Function Selection pin Special function P80 OSC1 IRQ2A P81 OSC2 IRQ3A P82 C1 P83 C2 P84 VLC3 P85 VLC2 Setup Function Register ANEN1 IRQIEN IRQISEL0 Bit name ANEN10 IRQI2EN IRQ2SEL 1 OSC1 0 1 0 IRQ2A 0 P80 Setup Function Register ANEN1 IRQIEN IRQISEL0 Bit name ANEN11 IRQI3EN IRQ3SEL 1 OSC2 0 1 0 IRQ3A 0 P81 ...

Page 247: ...n Table 7 12 6 P84 Function Selection Table 7 12 7 P85 Function Selection Setup Function Register ANEN1 Bit name ANEN12 1 C1 0 P82 Setup Function Register ANEN1 Bit name ANEN13 1 C2 0 P83 Setup Function Register ANEN1 Bit name ANEN14 1 VLC3 0 P84 Setup Function Register ANEN1 Bit name ANEN15 1 VLC2 0 P85 ...

Page 248: ...Chapter 7 I O Port VII 60 Port 8 ...

Page 249: ...VIII Chapter 8 8 bit Timer 8 ...

Page 250: ... TM5IOA P21 TM5IOB P73 Timer pulse output PWM output PWM output with additional pulses Pulse width measurement External Interrupt 0 IRQ0A P10 IRQ0B P60 External Interrupt 2 IRQ2A P80 IRQ2B P62 External Interrupt 4 IRQ4A P14 IRQ4B P72 IRQ4C P12 Cascade connection 16 bit counter 16 bit counter 16 bit counter Clock source HCLK HCLK 4 HCLK 16 HCLK 32 HCLK 64 SYSCLK 2 SYSCLK 4 SCLK TM0IO input HCLK HCL...

Page 251: ... U X HCLK TMnIO HCLK 16 HCLK 32 HCLK 64 SYSCLK 2 SYSCLK 4 SCLK HCLK 4 HCLK TMmIO HCLK 16 HCLK 64 HCLK 128 SYSCLK 2 SYSCLK 8 SCLK HCLK 4 TMmIRQ interrupt TMnIRQ interrupt TMnCK1 0 TMnMD register TMnPSC1 0 TMnBAS CKnMD register TMnOC register TMnBC register TMmOC register TMmBC register Overflow matching detection matching detection TMmCAS bit TMmMD register TMmCK1 0 TMmMD register TMmPSC1 0 TMmBAS ...

Page 252: ...mpare register VIII 8 TM2MD 0x03F84 R W Timer 2 mode register VIII 11 CK2MD 0x03F86 R W Timer 2 prescaler selection register VIII 6 TM2ICR 0x03FEC R W Timer 2 interrupt control register III 29 Timer 3 TM3BC 0x03F81 R Timer 3 binary counter VIII 8 TM3OC 0x03F83 R W Timer 3 compare register VIII 8 TM3MD 0x03F85 R W Timer 3 mode register VIII 12 CK3MD 0x03F87 R W Timer 3 prescaler selection register ...

Page 253: ... R W R W R W R W R W bp Bit name Description 7 to 6 Always read as 0 5 to 4 TM0ADD1 0 Position of additional pulse within 4 cycles of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle 3 TM0ADDEN PWM output with additional pulses control 0 Disabled 8 bit PWM output 1 Enabled 2 to 0 TM0PSC1 0 TM0BAS Clock source select 000 HCLK 4 010 HCL...

Page 254: ...les of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle 3 TM2ADDEN PWM output with additional pulses control 0 Disabled 8 bit PWM output 1 Enabled 2 to 0 TM2PSC1 0 TM2BAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 32 110 HCLK 64 X01 SYSCLK 2 X11 SYSCLK 4 bp 7 6 5 4 3 2 1 0 Bit name TM3PSC1 0 TM3BAS At reset 0 0 0 0 0 0 0 0 Ac...

Page 255: ...les of PWM basic waveform 00 No pulse 01 At second cycle 10 At first and third cycle 11 At first second and third cycle 3 TM4ADDEN PWM output with additional pulses control 0 Disabled 8 bit PWM output 1 Enabled 2 to 0 TM4PSC1 0 TM4BAS Clock source select 000 HCLK 4 010 HCLK 16 100 HCLK 32 110 HCLK 64 X01 SYSCLK 2 X11 SYSCLK 4 bp 7 6 5 4 3 2 1 0 Bit name TM5PSC1 0 TM5BAS At reset 0 0 0 0 0 0 0 0 Ac...

Page 256: ...03F70 TM1BC 0x03F71 TM2BC 0x03F80 TM3BC 0x03F81 TM4BC 0x03F90 TM5BC 0x03F91 Timer n binary counter is an 8 bit up counter If any data are written to the timer n compare register while the counter is stopped the timer n binary counter is cleared to 0x00 When reading the value of TMnBC register in cascade connection pair of registers TM1BC and TM0BC TM3BC and TM2BC TM5BC and TM4BC must be accessed s...

Page 257: ...ys read as 0 6 TM0POP Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High 5 TM0MOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P10 P60 4 TM0PWM Timer 0 operation mode control 0 Normal timer operation 1 PWM operation 3 TM0EN Timer 0 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM0CK1 0 ...

Page 258: ... At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R R W R W bp Bit name Description 7 5 Always read as 0 4 TM1CAS Timer 1 operation mode select 0 Normal timer operation 1 Cascade connection 3 TM1EN Timer 1 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM1CK1 0 Clock source select 00 HCLK 01 TM1PSC prescaler output 10 SCLK 11 TM1IO input ...

Page 259: ...6 TM2POP Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High 5 TM2MOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P80 P62 4 TM2PWM Timer 2 operation mode control 0 Normal timer operation 1 PWM operation 3 TM2EN Timer 2 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM2CK1 0 Clock source ...

Page 260: ... At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R R W R W bp Bit name Description 7 5 Always read as 0 4 TM3CAS Timer 3 operation mode select 0 Normal timer operation 1 Cascade connection 3 TM3EN Timer 3 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM3CK1 0 Clock source select 00 HCLK 01 TM3PSC prescaler output 10 SCLK 11 TM3IO input ...

Page 261: ... TM4POP Initial polarity of output signal select 0 Timer output Low High PWM High Low 1 Timer output High Low PWM Low High 5 TM4MOD Pulse width measurement control 0 Normal timer operation 1 Pulse width measurement P14 P72 P12 4 TM4PWM Timer 4 operation mode select 0 Normal timer operation 1 PWM operation 3 TM4EN Timer 4 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM4CK1 0 Clock sourc...

Page 262: ... At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R R W R W bp Bit name Description 7 5 Always read as 0 4 TM5CAS Timer 5 operation mode select 0 Normal timer operation 1 Cascade connection 3 TM5EN Timer 5 count enable 0 Disabled 1 Enabled 2 Always read as 0 1 0 TM5CK1 0 Clock source select 00 HCLK 01 TM5PSC prescaler output 10 SCLK 11 TM5IO input ...

Page 263: ...ted at the next count clock Then the timer n binary counter is cleared and restarts counting up from 0x00 The clock source can be selected depending on timers as shown in the table below When using SCLK as a clock source the timer counts at the falling edge of the count clock When using other clocks the timer counts at the rising edge of the count clock Clock source Time per Count Timer 0 Timer 1 ...

Page 264: ... count clock Then the binary counter starts counting up from the next count clock where the internal enable has been set C When the value of binary counter matches the setting value of compare register an interrupt request is generated at the next count clock Then the binary counter is cleared and restarts counting up D Even if the compare register is rewritten while the count operation is enabled...

Page 265: ... value When reading the value without waiting for 1 count cycle use the program to read the value of the binary counter multiple times In this case the read value is count value 1 II When changing the timer setting clock selection function switching etc wait for 1 count clock after setting the TMnMD TMnEN to 0 to stop the timer Then Restart the timer If the setting is switched during the timer ope...

Page 266: ...n clock HCLK or the prescaler output TMnPSC is selected as a clock source stop the timer before the mode transition After the mode transition activate the timer again In the SLOW HALT1 mode do not select HCLK or any clock generated from HCLK as a timer clock source When TMnOC is set to 00 clear TMnBC before starting the timer operation ...

Page 267: ... the timer counter TM0MD TM0EN 0 Disable the timer count operation 2 Disable the interrupt TM0ICR TM0IE 0 Disable the timer interrupt 3 Set the timer mode register TM0MD TM0PWM 0 TM0MD TM0MOD 0 Select the normal timer operation 4 TM0MD TM0CK1 0 01 Select the clock source 5 Set the prescaler CK0MD TM0PSC1 0 X0 CK0MD TM0BAS 1 Select SYSCLK 2 6 Set the interrupt cycle TM0OC 0xF9 Set the cycle of time...

Page 268: ... TMnBC matches the setting value of timer n compare register an interrupt request is generated at the next count clock For event count input clock of each timer refer to Table 8 1 1 Count Timing of TMnIO Input When TMnIO input is selected TMnIO input becomes the count clock of Timer n The binary counter starts counting up at the falling edge of the TMnIO input signal Figure 8 4 1 Count Timing of T...

Page 269: ...ad the binary counter value after the timer has stopped set the TMnMD TMnEN to 0 wait for 1 count cycle and read the value When reading the value without waiting for 1 count cycle use the program to read the value of the binary counter multiple times In this case the read value is count value 1 II When changing the timer setting clock selection function switching etc wait for 1 count clock after s...

Page 270: ... interrupt TM0ICR TM0IE 0 Disable the timer interrupt 3 Select the event input TMIOSEL0 TM0IOSEL0 0 Select the event clock input pin Chapter 7 I O Port 4 P0DIR P0DIR5 0 5 Set the interrupt cycle TM0OC 0x04 Set the interrupt generation cycle 6 Set the timer mode register TM0MD TM0PWM 0 TM0MD TM0MOD 0 Select the timer normal operation 7 TM0MD TM0CK1 0 11 Select TM0IO input as the count clock source ...

Page 271: ...ich is set in TMnOC Refer to Table 8 1 1 for the pulse output pin Count Timing of Timer Pulse Output Figure 8 5 1 Count Timing of Timer Pulse Output A The signal with twice the cycle which is set in TMnOC is output from TMnIO pin B When the value of TMnBC matches the setting value of TMnOC TMnBC is cleared to 0x00 and TMnIO output timer output is inverted N 00 01 N 1 N Count clock TMnEN bit Compar...

Page 272: ...is stopped the timer output turns to Low Step Setting Register Description 1 Disable the timer counter TM0MD TM0EN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN0 TM0OEN 1 Select the timer output pin Chapter 7 I O Port 3 P0DIR P0DIR5 1 4 Set the timer mode register TM0MD TM0PWM 0 TM0MD TM0MOD 0 Select the timer normal operation 5 TM0MD TM0CK1 0 01 Select the prescaler as ...

Page 273: ...gure 8 6 1 Count Timing of PWM Output at Normal When TMnPOP bit is 0 A PWM output is High while TMnBC counts up from 0x01 to the setting value of TMnOC B PWM output changes to Low when TMnBC matches the setting value of TMnOC then TMnBC contin ues counting up until it overflows As for the initial setting the PWM output is changed from Low to High when setting the TMnMD TMnPWM when TMnPOP bit 0 to ...

Page 274: ...the compare register is 0xFF Figure 8 6 3 Count Timing of PWM Output when the compare register is 0xFF When TMnMD TMnEN is 0 timer function is stopped PWM output is High 00 N 1 N 2 FE FF Count clock TMnEN bit Compare register Binary counter 00 01 N 1 N 1 N 00 01 N 1 N TMnIO output PWM output Count clock TMnEN bit Compare register Binary counter TMnIO output PWM output FF N 1 N 2 FE FF 00 01 N 1 N ...

Page 275: ... timer counter TM0MD TM0EN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN0 TM0OEN 1 Select the timer output pin Chapter 7 I O Port 3 P0DIR P0DIR5 1 4 Set the timer mode register TM0MD TM0PWM 1 TM0MD TM0MOD 0 TM0MD TM0POP 0 Select the PWM operation 5 TM0MD TM0CK1 0 01 Select the prescaler as the clock source 6 Set the prescaler CK0MD TM0PSC1 0 X0 CK0MD TM0BAS 1 Select SYSC...

Page 276: ...TMnADD1 0 Figure 8 6 5 shows the setting value of CKnMD TMnADD1 0 and the location of additional pulses Figure 8 6 5 Count timing of PWM Output with Additional Pulses Method An interrupt occurs at the 4th cycle of the PWM basic waveform CKnMD TMnADD1 0 00 No additional pulse CKnMD TMnADD1 0 11 CKnMD TMnADD1 0 01 CKnMD TMnADD1 0 10 Interrupt request PWM basic waveform 4 cycles additional pulse addi...

Page 277: ...se width by reading the count value of the timer For pulse width measurement pins refer to Table 8 1 1 Count Timing of Simple Pulse Width Measurement Figure 8 7 1 Count Timing of Simple Pulse Width Measurement The internal enable signal is generated while the timer is in active by setting TMnMD TMnEN to 1 and the sig nal sampled at the count clock is Low The signal is input from an external interr...

Page 278: ...e Low period of IRQ0 input can be detected by reading the value of TM0BC in the interrupt process Step Setting Register Description 1 Disable the timer counter TM0MD TM0EN 0 Disable the timer count operation 2 Set the timer mode register TM0MD TM0PWM 0 TM0MD TM0MOD 1 Select the pulse width measurement function 3 TM0MD TM0CK1 0 01 Select the prescaler as the clock source 4 Set the prescaler CK0MD T...

Page 279: ...er 2 connected connected with Timer 3 Timer 4 connected with Timer 5 The timer functions in 16 bit cascade connection are listed in Table 8 8 1 Table 8 8 1 Timer Functions in 16 bit Cascade Connection Timer 0 to Timer 1 Timer 2 to Timer 3 Timer 4 to Timer 5 Interrupt source TM1IRQ TM3IRQ PERI0IRQ0 Event count TM0IOA P05 TM0IOB P03 TM2IOA P05 TM2IOB P02 TM4IOA P34 TM4IOB P01 Timer output TM1IOA P55...

Page 280: ...th Timer 3 in cascade a timer pulse and an interrupt request are output from Timer 3 Low fixed data are output from Timer 2 as the timer pulse Timer 2 interrupt should be disabled though any interrupt request of Timer 2 is not generated When using Timer 4 connected with Timer 5 in cascade a timer pulse and an interrupt request are output from Timer 5 Low fixed data are output from Timer 4 as the t...

Page 281: ...per 8 bits timer Lower 8 bits timer TM0ICR TM0IE 0 TM1ICR TM1IE 0 Disable the timer interrupt 2 Set the timer mode register Lower 8 bits timer TM0MD TM0PWM 0 TM0MD TM0MOD 0 Select the timer normal operation 3 Set the cascade connection TM1MD TM1CAS 1 Select the cascade connection 3 Set the clock source Lower 8 bits timer TM0MD TM0CK1 0 01 Select the prescaler as the clock source 4 Set the prescale...

Page 282: ...Chapter 8 8 bit Timer VIII 34 8 bit Timer Cascade Connection ...

Page 283: ...IX Chapter 9 16 bit Timer 9 ...

Page 284: ...A P07 TM9IOB P20 TM9IOC P00 Timer pulse output Standard PWM output with variable duty High precision PWM output with variable duty cycle Standard IGBT output with variable duty TM7IOA P04 TM7IOB P34 TM7IOC P03 TM8IOA P57 TM8IOB P06 TM8IOC P02 High precision IGBT output with variable duty cycle Capture function Clock source HCLK HCLK 2 HCLK 4 HCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 16 TM7IO input T...

Page 285: ...on TMnOC2IRQ M U X overflow M U X M U X TMnIRQ 16bit Compare Register2 TMnOC2H TMnOC2L 16bit Preset Register2 TMnPR2H TMnPR2L 8bit Dead time Counter 1 Timer PWM output generation IGBT output generation 1 TMnIO HCLK HCLK 2 HCLK 4 HCLK 16 SCLK SCLK 2 SCLK 4 SCLK 16 SYSCLK SYSCLK 2 SYSCLK 4 SYSCLK 16 TMnIO input TMnIO input 2 TMnIO input 4 TMnIO input 16 Match detection 1 Function of Timer 7 only 8bi...

Page 286: ...ad time preset register 2 IX 9 TM7MD3 0x03FBE R W Timer 7 mode register 3 IX 12 TM7MD4 0x03F9E R W Timer 7 mode register 4 IX 13 TM7ICR 0x03FEF R W Timer 7 interrupt control register III 29 TM7OC2ICR 0x03FF0 R W Timer 7 compare register 2 match interrupt control register III 29 Timer 8 TM8BCL 0x03FB0 R Timer 8 binary counter lower 8 bits IX 8 TM8BCH 0x03FB1 R Timer 8 binary counter upper 8 bits IX...

Page 287: ...gister lower 8 bits IX 8 TM9ICH 0x03FC7 R Timer 9 input capture register upper 8 bits IX 8 TM9MD1 0x03FC8 R W Timer 9 mode register 1 IX 18 TM9MD2 0x03FC9 R W Timer 9 mode register 2 IX 19 TM9OC2L 0x03FCA R Timer 9 compare register 2 lower 8 bits IX 6 TM9OC2H 0x03FCB R Timer 9 compare register 2 upper 8 bits IX 6 TM9PR2L 0x03FCC R W Timer 9 preset register 2 lower 8 bits IX 7 TM9PR2H 0x03FCD R W T...

Page 288: ...M9OC1L 0x03FC2 Timer n Compare Register 1 Upper 8 bits TM7OC1H 0x03FA3 TM8OC1H 0x03FB3 TM9OC1H 0x03FC3 Timer n Compare Register 2 Lower 8 bits TM7OC2L 0x03FAA TM8OC2L 0x03FBA TM9OC2L 0x03FCA Timer n Compare Register 2 Upper 8 bits TM7OC2H 0x03FAB TM8OC2H 0x03FBB TM9OC2H 0x03FCB bp 7 6 5 4 3 2 1 0 Bit name TMnOC1L7 0 At reset X X X X X X X X Access R R R R R R R R bp 7 6 5 4 3 2 1 0 Bit name TMnOC1...

Page 289: ...Upper 8 bits TM7PR1H 0x03FA5 TM8PR1H 0x03FB5 TM9PR1H 0x03FC5 Timer n Preset Register 2 Lower 8 bits TM7PR2L 0x03FAC TM8PR2L 0x03FBC TM9PR2L 0x03FCC Timer n Preset Register 2 Upper 8 bits TM7PR2H 0x03FAD TM8PR2H 0x03FBD TM9PR2H 0x03FCD Timer 7 preset register 1 and 2 must not be changed during IGBT operation bp 7 6 5 4 3 2 1 0 Bit name TMnPR1L7 0 At reset X X X X X X X X Access R W R W R W R W R W ...

Page 290: ...M9BCL 0x03FC0 Timer n Binary Counter Upper 8 bits TM7BCH 0x03FA1 TM8BCH 0x03FB1 TM9BCH 0x03FC1 Input capture registers are registers that hold the value loaded from the binary counters at a capture trigger Timer n Input Capture Register Lower 8 bits TM7ICL 0x03FA6 TM8ICL 0x03FB6 TM9ICL 0x03FC6 Timer n Input Capture Register Upper 8 bits TM7ICH 0x03FA7 TM8ICH 0x03FB7 TM9ICH 0x03FC7 bp 7 6 5 4 3 2 1...

Page 291: ...er 2 TM7DPR2 0x03FAF Timer 7 preset register 1 and 2 must not be changed during IGBT operating bp 7 6 5 4 3 2 1 0 Bit name TM7DPR1 7 TM7DPR1 6 TM7DPR1 5 TM7DPR1 4 TM7DPR1 3 TM7DPR1 2 TM7DPR1 1 TM7DPR1 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp 7 6 5 4 3 2 1 0 Bit name TM7DPR2 7 TM7DPR2 6 TM7DPR2 5 TM7DPR2 4 TM7DPR2 3 TM7DPR2 2 TM7DPR2 1 TM7DPR2 0 At reset 0 0 0 0 0 0 0 0 ...

Page 292: ... 0 0 Access R R W R W R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 T7ICEDG1 Select capture trigger edge 0 Falling edge 1 Rising edge 5 TM7CL Timer output enable 0 Enabled 1 Disabled reset 4 TM7EN Control timer count 0 Disabled 1 Enabled 3 2 TM7PS1 0 Select count clock 00 1 1 clock 01 1 2 clock 10 1 4 clock 11 1 16 clock 1 0 TM7CK1 0 Select clock source 00 HCLK 01 SYSCLK 10 TM7I...

Page 293: ...7PWMSL Select PWM mode 0 Set duty through TM7OC1 1 Set duty through TM7OC2 5 TM7BCR Select timer clear source 0 Overflow by full count 1 Match between TM7BC and TM7OC1 4 TM7PWM Select timer output waveform 0 Timer output 1 PWM output 3 TM7IRS1 Select timer interrupt source 0 Counter clear 1 Match of TM7BC and TM7OC1 2 T7ICEN Input capture operation enable 0 Disabled 1 Enabled 1 0 T7ICT1 0 Select c...

Page 294: ...0 0 0 Access R W R R W R W R W R W R W R W bp Bit name Description 7 TM7CKSMP Select sampling clock for capture 0 Count clock 1 SYSCLK 6 Always read as 0 5 TM7CKEDG Select count edge of TM7IO 0 Falling edge 1 Both edges 4 T7IGBTTR Select trigger level 0 High 1 Low 3 T7IGBTDT Input timing of IGBT dead time 0 Falling edge 1 Rising edge 2 T7IGBTEN IGBT enable 0 Disabled 1 Enabled 1 0 T7IGBT1 0 Select...

Page 295: ...he TM7MD1 TM7EN must not be changed at the same time as the other bit bp 7 6 5 4 3 2 1 0 Bit name T7ONE SHOT T7NODED T7ICT2 T7CAP CLR At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R R W R W bp Bit name Description 7 5 Always read as 0 4 T7ONESHOT Select pulse 0 Continuous pulse 1 One shot pulse 3 T7NODED Set dead time 0 Yes 1 No 2 Always read as 0 1 T7ICT2 Select capture trigger 0 Timer 0 interrup...

Page 296: ...R W R W R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 T8ICEDG1 Select capture trigger edge 0 Falling edge 1 Rising edge 5 TM8CL Timer output enable 0 Enabled 1 Disabled reset 4 TM8EN Control timer count 0 Disabled 1 Enabled 3 2 TM8PS1 0 Select count clock 00 1 1 clock 01 1 2 clock 10 1 4 clock 11 1 16 clock 1 0 TM8CK1 0 Select clock source 00 HCLK 01 SYSCLK 10 TM8IO input 11 SCL...

Page 297: ...MSL Select PWM mode 0 Set duty through TM8OC1 1 Set duty through TM8OC2 5 TM8BCR Select timer clear source 0 Overflow by full count 1 Match between TM8BC and TM8OC1 4 TM8PWM Select timer output waveform 0 Timer output 1 PWM output 3 TM8IRS1 Select timer interrupt source 0 Counter clear 1 Match between TM8BC and TM8OC1 2 T8ICEN Input capture operation enable 0 Disabled 1 Enabled 1 0 T8ICT1 0 Select...

Page 298: ...set 0 0 0 0 0 0 0 0 Access R W R R R W R W R W R W R bp Bit name Description 7 TM8CKSMP Select sampling clock for capture 0 Count clock 1 SYSCLK 6 5 Always read as 0 4 TM8CKEDG Select count edge of TM8IO 0 Falling edge 1 Both edges 3 TM8SEL Select output 0 Timer 8 output 1 IGBT output 2 TM8PWMF Control PWM output while Timer 8 is stopped 0 Low 1 High 1 TM8PWMO Select polarity of Timer 8 PWM output...

Page 299: ...opped Set the Timer 8 mode registers while the TM8MD1 TM8EN is 0 And the TM8MD1 TM8EN must not be changed at the same time as the other bit bp 7 6 5 4 3 2 1 0 Bit name T8ICT2 T8CAPCLR At reset 0 0 0 0 0 0 0 0 Access R R R R R R R W R W bp Bit name Description 7 2 Always read as 0 1 T8ICT2 Select capture trigger 0 Timer 0 interrupt 1 Timer 1 interrupt 0 T8CAPCLR Binary counter clear enable at captu...

Page 300: ...R W R W R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 T9ICEDG1 Select capture trigger edge 0 Falling edge 1 Rising edge 5 TM9CL Timer output enable 0 Enabled 1 Disabled reset 4 TM9EN Control timer count 0 Disabled 1 Enabled 3 2 TM9PS1 0 Select count clock 00 1 1 clock 01 1 2 clock 10 1 4 clock 11 1 16 clock 1 0 TM9CK1 0 Select clock source 00 HCLK 01 SYSCLK 10 TM9IO input 11 SCL...

Page 301: ...lect PWM mode 0 Set duty through TM9OC1 1 Set duty through TM9OC2 5 TM9BCR Select timer clear source 0 Overflow by full count 1 Match between TM9BC and TM9OC1 4 TM9PWM Select timer output waveform 0 Timer output 1 PWM output 3 TM9IRS1 Select timer interrupt source 0 Counter clear 1 Match of TM9BC and TM9OC1 2 T9ICEN Input capture operation enable 0 Disabled 1 Enabled 1 0 T9ICT1 0 Select capture tr...

Page 302: ... TM9CKSMP to 0 Set the Timer 9 mode registers while the TM9MD1 TM9EN is 0 And the TM9MD1 TM9EN must not be changed at the same time as the other bit bp 7 6 5 4 3 2 1 0 Bit name TM9CKSMP At reset 0 0 0 0 0 0 0 0 Access R W R R R R R R R bp Bit name Description 7 TM9CKSMP Select sampling clock for capture 0 Count clock 1 SYSCLK 6 0 Always read as 0 ...

Page 303: ... bit access instruction MOVW or write data to TMnIC with a software function When using the MOVW instruction indeterminate data during counting may be read So read the register value several times and confirm those data are identical When using the capture function writing to TMnIC can capture the count value of TMnBC to the TMnIC to read the count value during counting precisely For more informat...

Page 304: ...m the next count clock where the internal enable has been set The count operation is executed at the rising edge of the count clock C Even if the preset register is rewritten while the count operation is enabled the TMnEN bit is set to 1 the binary counter is not changed D When the value of binary counter matches the setting value of compare register 1 the setting value of the preset register is l...

Page 305: ...r starts the timer interrupt request bit should be cleared When TMnBC is used as a free counter that counts from 0x0000 to 0xFFFF set TMnOC1 to 0xFFFF or set the TMnMD2 TMnBCR to 0 Do not change the TMnMD TMnEN simultaneously with other bits to avoid any error in oper ation In 16 bit timer operation the internal enable signal becomes ON status at the rising edge of the first count clock after the ...

Page 306: ...D1 TM7EN 0 Disable the timer count operation 2 Disable the interrupt TM7ICR TM7IE 0 Disable the timer interrupt 3 Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source 4 TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 01 Select the clock source 5 Set the interrupt cycle TM7PR1 0x03E7 Set the cycle of timer interrupt Setup value 1000 1 999 0x03E7 6 Set the interrupt level TM7ICR TM7LV1 0 Ref...

Page 307: ... divided by 1 not divided 2 4 or 16 The event count input pin is shown in Table 9 1 1 Count Timing of TMnIO Input The binary counter counts up at the falling edge of TMnIO input signal that is divided or not Figure 9 4 1 Count Timing TMnIO Input TMnIO input TMnEN bit Internal enable Compare register Binary counter Interrupt request N 0000 0001 0002 N 1 N 0000 0001 ...

Page 308: ...ng TMnIO input be sure to set each mode register and preset register after select ing SYSCLK as a count clock source Then select TMnIO input to start a timer As for the 16 bit timer only when using TMnIO input it is possible to return from STOP HALT2 HALT3 mode When using the event input TMnIO input clear TMnBC before starting the timer operation In the event count the internal enable signal becom...

Page 309: ...lecting the both edge count the count is executed only at the normal operation mode with high speed oscillation Also when setting the TMnMD3 TMnCKSMP to 1 to select the system clock SYSCLK the count is not executed correctly Input signal from TMnIO should be set to the cycle more than twice the HCLK When the other signal with the shorter cycle is input the count may not be executed correctly N 000...

Page 310: ...ble the timer interrupt 3 Select the event input TMIOSEL1 TM7IOSEL1 0 00 Select the event clock input pin Chapter 7 I O Port 4 P0DIR P0DIR4 0 5 Set the timer mode register TM7MD1 TM7CK1 0 01 TM7MD1 TM7PS1 0 00 Select SYSCLK as the clock source 6 Set the interrupt cycle TM7PR1 0x0003 Set the interrupt generation cycle 7 Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source 8 TM7...

Page 311: ...l timer interrupt generation sources and timer pulse output cycles Table 9 5 1 16 bit Timer Interrupt Generation Source and Timer Pulse Output Cycle Count Timing of 16 bit Timer Pulse Output Figure 9 5 1 Count Timing of 16 bit Timer Pulse Output TMnMD2 Interrupt source Timer pulse output cycle TMnIRS1 TMnBCR 1 1 TMnOC1 compare match Twice the value of TMnOC1 0 1 TMnOC1 compare match Twice the valu...

Page 312: ...for clock source and set 1 2 cycle 100 kHz in the Timer 7 compare register HCLK at fHCLK 8 MHz is selected as a clock source The setup procedure and its description are shown below Step Setting Register Description 1 Disable the timer counter TM7MD TM7EN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN1 TM7OEN 1 Select the timer output pin Chapter 7 I O Port 3 P0DIR P0DIR4 ...

Page 313: ...Table 9 1 1 Count Timing of Standard PWM Output at Normal Figure 9 6 1 Count Timing of Standard PWM Output at Normal As for PWM output waveform A PWM output is High while the binary counter counts up from 0x0000 to the setting value of the com pare register B PWM output changes to Low when the binary counter matches the setting value of the compare register then the binary counter continues counti...

Page 314: ...WM output can be selected with the TM8MD3 TM8PWMO Count Timing of Standard PWM Output when compare register 1 is set to 0x0000 Figure 9 6 2 Count Timing of Standard PWM Output when compare register 1 is set to 0x0000 The PWM output is High while the counter is stopped by setting TMnMD1 TMnEN to 0 0000 N 1 N 2 FFFE FFFF Count clock TMnEN bit Compare register 1 Binary counter TMnIO output PWM output...

Page 315: ...an be selected as a PWM output reset source Low output with the TMnMD2 TnPWMSL The PWM output at the initial state for Timer 7 and 9 is Low It changes to High at the time the PWM operation is selected by setting the TMnMD2 TMnPWM For Timer 8 it is in accordance with the setting of the TM8MD2 TM8PWMF and TM8MD2 TM8PWM0 When restarting the PWM operation after PWM operation has been stopped write dat...

Page 316: ... the time the PWM opera tion is selected by setting TM7MD2 TM7PWM to 1 Step Setting Register Description 1 Disable the timer counter TM7MD TM7EN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN1 TM7OEN 1 Select the timer output pin Chapter 7 I O Port 3 P0DIR P0DIR4 1 4 Set the timer mode register TM7MD2 TM7PWM 1 Select the PWM output 5 TM7MD2 TM7BCR 0 Select the TM7BC clear...

Page 317: ... at Normal Figure 9 7 1 Count Timing of High Precision PWM Output at Normal PWM output waveform A PWM output is High while the binary counter counts up from 0x0000 to the setting value of the com pare register 2 B PWM output changes to Low when the binary counter matches the setting value of the compare register 2 then the binary counter continues counting up until the binary counter is cleared by...

Page 318: ...en compare register 2 is set to 0x0000 Figure 9 7 2 Count Timing of High Precision PWM Output when compare register 2 is set to 0x0000 The PWM output is High while the counter is stopped by setting TMnMD1 TMnEN to 0 N N 1 N Count clock TMnEN bit Compare register 1 Binary counter 0000 0001 0000 0001 TMnIO output PWM output 0000 Compare register 2 ...

Page 319: ... as the binary counter clear source and the PWM set source to High state Also set the TMnMD2 TnPWMSL to 1 to select TMnOC2 compare match as the PWM reset source to Low state The PWM output at the initial state is Low It changes to High at the time the PWM opera tion is selected by setting the TMnMD2 TMnPWM When outputting the high precision PWM set the values of TMnOC1 and 2 as follow TMnOC2 TMnOC...

Page 320: ...MD TM7EN 0 Disable the timer count operation 2 Select the timer output pin TMIOEN1 TM7OEN 1 Select the timer output pin Chapter 7 I O Port 3 P0DIR P0DIR4 1 4 Set the timer mode register TM7MD2 TM7PWM 1 Select the PWM output 5 TM7MD2 TM7BCR 1 TM7MD2 T7PWMSL 1 Select the TM7BC clear source and the duty determination source of PWM output 6 TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 01 Select HCLK 2 as the co...

Page 321: ...r Input capture trigger is generated by the external interrupt input signal Set TMnMD1 and TMnMD2 to select the capture trigger Table 9 8 1 show the available types of capture trigger and bit settings Table 9 8 1 Capture Trigger Capture trigger source TMnMD2 TMnMD1 TnICT1 0 TnICEDG0 TnICEDG1 IRQ0 falling edge 00 IRQ0 1 0 IRQ0 rising edge 00 IRQ0 1 1 IRQ0 both edges 00 IRQ0 0 IRQ1 falling edge 01 I...

Page 322: ...mers Timer 7 9 is generated by sampling at the ris ing edge of the capture clock selected with the TMnMD3 TMnCKSMP Therefore even if a capture trigger is input the value of the binary counter is not loaded to the capture register until at the 2nd rising edge of the capture clock from the capture trigger If the clock which is slower than the CPU operation speed fSYSCLK is used as the timer source c...

Page 323: ...ge of the interrupt signal The other count timing is the same as that of the timer operation When the binary counter is used as a free run counter which counts from 0x0000 to 0xFFFF set Compare register 1 to 0xFFFF or set the TMnMD2 TMnBCR to 0 Even if an event occurs before the value of the input capture register is read out the value of the input capture register is rewritten A capture trigger s...

Page 324: ...lue of the binary counter to the capture register since a capture trigger is sampled at the capture clock In the initial state after releasing the reset the setting of the external interrupt signal as a trig ger is disabled Set the TMnMD2 TnICEN to 1 to enable the trigger of the external interrupt signal ...

Page 325: ... with the capture clock Synchronizing with this capture trigger the value of the binary counter is loaded to the input capture regis ter The value loaded to the capture register is the binary counter value at the falling edge of the capture trigger The other count timing is the same as that of the timer operation On hardware there is no bit to disable the capture operation triggered by software wr...

Page 326: ...nMD4 to select the capture trigger When selecting the Timer 0 or 1 interrupt as a capture trigger the selected edge is invalid A capture trigger is generated by sampling the interrupt signal of Timer 0 or 1 at the capture clock Therefore the edge of the external interrupt input signal may not be detected when an inter val of interrupt input signal is shorter than capture clock cycle To prevent thi...

Page 327: ...eared at a capture operation When clearing the binary counter at a capture operation set the TMnMD4 TnCAPCLR to 1 However the binary counter can be cleared only during the timer count operation Figure 9 8 4 Binary Counter Clear Function at Capture Timer 7 and Timer 8 Count clock TMnEN bit Compare register 1 Binary counter Capture register 0000 0001 0002 N 0001 0002 0003 0004 0000 0001 0002 0003 00...

Page 328: ... TM7MD TM7EN 0 Disable the timer count operation 2 Disable the interrupt TM7ICR TM7IE 0 Disable the timer interrupt 3 Set the timer mode register TM7MD2 TM7BCR 1 Select the TM7BC clear source 4 TM7MD1 TM7CK1 0 00 TM7MD1 TM7PS1 0 00 Select HCLK as the count clock source 5 Set the compare register TM7PR1 0xFFFF Setup data in TM7PR1 is loaded to TM7OC1 6 Set the timer mode register TM7MD2 T7ICT1 0 00...

Page 329: ... To control the activation with the instruction select TM7EN count operation In that case the timer count oper ation and IGBT output are controlled with the TM7MD1 TM7EN When setting the bit to 1 to start counting the count operation continues until the bit is set to 0 to stop counting Be sure to set the TM7MD3 T7IGBT0 1 before setting the TM7MD1 TM7EN 16 bit Standard IGBT Output Operation Timer 7...

Page 330: ...y counter counts up from 0x0000 to the TM7OC2 compare match the IGBT output is High Only for the 1st cycle of counting the output is High from 0x0001 C After the TM7OC2 compare match the output changes to Low and the binary counter continues counting up until it overflows D When the binary counter overflows the IGBT output returns to High E When the IGBT trigger becomes invalid the timer is initia...

Page 331: ...egister 1 0xFFFF When using the IGBT standard output set the TM7MD2 TM7BCR to 0 to select the full count overflow as the binary counter clear source and the IGBT output set source to High state The TM7OC1 compare match or TM7OC2 compare match can be selected for the IGBT out put reset source to Low state by setting the TM7MD2 T7PWMSL 0000 N 1 N 2 FFFE FFFF Count clock TM7EN bit Compare register Bi...

Page 332: ...pin TMIOEN1 TM7OEN 1 Select the IGBT output pin Chapter 7 I O Port 3 P0DIR P0DIR4 1 4 Set the timer mode register TM7MD3 T7IGBTEN 1 TM7MD2 TM7PWM 1 TM7MD1 TM7CL 0 Enable the IGBT output 5 TM7MD2 TM7BCR 0 Select the TM7BC clear source 6 TM7MD3 T7IGBT1 0 01 Select the IGBT trigger source 7 TM7MD3 T7IGBTTR 1 Select the IGBT trigger level 8 TM7MD4 T7NODED 1 Select No as the dead time 9 TM7MD1 TM7CK1 0...

Page 333: ...0 1 The IGBT output starts by detecting the trigger input level When setting the TM7MD3 T7IGBTTR to 1 to select the rising edge the count operation is executed while the corresponding interrupt pin is High When setting the TM7MD3 T7IGBTTR to 0 to select the falling edge the count operation is executed while the corresponding interrupt pin is Low To control the activation with the instruction selec...

Page 334: ...precision IGBT output function can be used in Timer 7 Table 9 10 1 IGBT Output Pin Table 9 10 2 IGBT Trigger One shot Pulse Output One shot pulse can be output by setting the TM7MD4 T7ONESHOT to 1 Timer 7 IGBT output pin TM7IOA output TM8IOA output TM7IOB output TM8IOB output TM7IOC output TM8IOC output TM7MD3 T7IGBT1 0 T7IGBTTR IRQ0 falling edge 01 IRQ0 1 IRQ0 rising edge 01 IRQ0 0 IRQ1 falling e...

Page 335: ...from 0x0000 to the TM7OC2 compare match the IGBT output is High Only for the 1st cycle of counting the output is High from 0x0001 C After the TM7OC2 compare match the output changes to Low The binary counter continues counting up until it is cleared by the TM7OC1 compare match D When the binary is cleared the IGBT output returns to High E When the IGBT trigger becomes invalid the timer is initiali...

Page 336: ...w Count timing of High Precision IGBT Output when compare register 2 compare register 1 Timer 7 Figure 9 10 3 Count timing of High Precision IGBT Output when compare register 2 compare register 1 N 0000 0000 0001 0002 N 1 N 0001 0000 L 1 L 0000 IGBT trigger TM7IO output IGBT output TM8IO output IGBT output Count clock TM7EN bit Compare register 1 Compare register 2 Binary counter N N 0000 0001 000...

Page 337: ...tial state becomes Low when setting the TM7MD3 T7IGBTEN to select the IGBT output It changes to High at the second count clock cycle from the trigger input When using the high precision IGBT output set the values of TM7OC1 and 2 as follow TM7OC2 TM7OC1 If TMnOC2 TMnOC1 the IGBT output is fixed to High One shot Pulse Output of High Precision IGBT Normal Timer 7 Figure 9 10 4 One shot Pulse Output o...

Page 338: ...ion IGBT when compare register 2 compare register 1 Timer 7 Figure 9 10 6 One shot Pulse Output of High Precision IGBT when compare register 2 compare register 1 Count Clock TM7EN Flag Compare Register 1 Compare Register 2 IGBT Trigger Binary Counter 0000 0001 0002 TM7IO output IGBT output N 1 N 0000 TM8IO output IGBT output N 0000 0000 0001 0002 N 1 N 0000 N N IGBT trigger TM7IO output IGBT outpu...

Page 339: ...7MD2 TM7BCR 0 TM7MD2 T7PWMSL 1 Select the TM7BC clear source and the duty determination source of IGBT output 7 TM7MD4 T7NODED 1 Select No as the dead time 8 TM7MD3 T7IGBT1 0 01 Select the IGBT trigger source 9 Set the external interrupt IRQ0ICR REDG0 1 Set the external interrupt valid edge 10 Set the timer mode register TM7MD3 T7IGBTTR 0 TM7MD2 T7ICEDG0 1 Select the IGBT trigger level and IGBT tr...

Page 340: ...ecuted while the corresponding interrupt pin is Low To control the activation with the instruction select TM7EN count operation In that case the timer count oper ation and IGBT output are controlled with the TM7MD1 TM7EN When setting the bit to 1 to start counting the count operation continues until the bit is set to 0 to stop counting Be sure to set the TM7MD3 T7IGBT0 1 before setting the TM7MD1 ...

Page 341: ...Dead Time Timer 7 Figure 9 11 1 Count Timing of IGBT Output with Dead Time 01 00 00 00 00 00 00 00 m m m 1 m 1 01 n 1 n n 1 m 1 M M 1 M 2 0000 0000 0001 0000 0002 0001 N N 1 N 2 Count clock IGBT trigger TM7PR1 TM7PR2 TM7DPR1 TM7DPR2 TM7BC TM7I0 TM8I0 Dead time counter M N m n A B C D E F G ...

Page 342: ... as follow TM7OC2 TM7OC1 If TMnOC2 TMnOC1 the IGBT output are at the falling edge setting TM7IO fixed to Low TM8IO fixed to Low If the IGBT trigger is enabled before 2 count clock cycles elapsed after the IGBT trigger is disabled the preset register data set during the IGBT operation may not be loaded to the compare register or the dead time preset register data set during the IGBT operation may n...

Page 343: ... 2 IGBT One shot Pulse Output Timing with dead time Count clock TM7EN bit Compaer register 1 Compare register 2 Dead time compaer register 1 Dead time compaer register 2 N M n m IGBT trigger Dead time counter 1 Dead time counter 2 Binary counter 0000 0001 0002 00 01 n 1 n 00 TM7IO output IGBT output TM8IO output IGBT output M 1 M M 2 01 00 M 1 m m 1 00 N 1 N N 1 ...

Page 344: ...urce 4 TM7MD3 T7IGBTTR 0 TM7MD2 T7ICEDG0 1 Select the IGBT trigger level and IGBT trigger edge 5 TM7MD3 T7IGBTDT 0 Select the dead time input timing 6 Set the external interrupt IRQISEL0 IRQ0SEL 0 IRQIEN IRQI0EN 1 Enable the external interrupt pin 7 Set the interrupt level IRQ0ICR IRQ0LV1 0 Refer to 3 1 3 Maskable Interrupt Control Register Setup 8 Enable the interrupt IRQ0ICR IRQ0IE 1 9 Set the t...

Page 345: ...eared by the TM7OC1 compare match The IGBT output waveform with dead time is output from the TM7IO pin The inverted IGBT output waveform with dead time is output from the TM8IO pin 13 Set the timer mode register TM7MD3 T7IGBTEN 1 TM7MD2 TM7PWM 1 TM8MD3 TM8SEL 1 TM7MD1 TM7CL 0 Enable the IGBT output 14 Select the IGBT output pin TMIOEN1 TM7OEN 1 TMIOEN1 TM8OEN 1 P0DIR P0DIR4 1 P5DIR P5DIR7 1 Select...

Page 346: ...Chapter 9 16 bit Timer IX 64 IGBT Output with Dead Time ...

Page 347: ...X Chapter 10 General Purpose Time Base Free Running Timer 10 ...

Page 348: ...rce PERI0IRQ2 PERI0IRQ1 Clock source HCLK SCLK HCLK SCLK SYSCLK HCLK 27 1 HCLK 213 1 SCLK 27 2 SCLK 213 2 Interrupt generation cycle 27 1 fHCLK 28 1 fHCLK 29 1 fHCLK 210 1 fHCLK 212 1 fHCLK 213 1 fHCLK 214 1 fHCLK 215 1 fHCLK 27 1 fSCLK 28 1 fSCLK 29 1 fSCLK 210 1 fSCLK 212 1 fSCLK 213 1 fSCLK 214 1 fSCLK 215 1 fSCLK The interrupt generation cycle is decided by the arbitrary value written to TM6OC...

Page 349: ...Base Timer 0 7 TM6CK0 TM6CK1 TM6CK2 TM6IR0 TM6CK3 TM6MD TM6BC RST TM6OC match detection Read Write Read M U X M U X SCLK M U X M U X HCLK SYSCLK TM6IR1 TM6IR2 TM6CLRS PERI0IRQ1 HCLK SCLK 15 1 2 13 12 1 2 1 2 9 1 2 8 1 2 10 1 2 7 1 2 ST PERI0IRQ2 TBCLR Write only 0 7 TM6EN TBEN TM6BEN 14 1 2 Time base timer 8 bit counter Compare register Timer 6 8 bit free running timer ...

Page 350: ...e Page Timer 6 TM6BC 0x03F78 R Timer 6 binary counter X 5 TM6OC 0x03F79 R W Timer 6 compare register X 5 TM6MD 0x03F7A R W Timer 6 mode register X 7 TM6BEN 0x03F7C R W Timer 6 enable register X 6 PERI0ICR 0x03FFD R W Peripheral function Group 0 interrupt level control register III 24 PERI0EN 0x03FDC R W Peripheral function Group 0 interrupt enable register III 25 PERI0DT 0x03FDD R W Peripheral fun...

Page 351: ...Counter TM6BC 0x03F78 Timer 6 Compare Register TM6OC 0x03F79 The time base timer can be reset by the software The time base timer can be cleared by writing an arbitrary value to the time base timer clear control register TBCLR Time Base Timer Clear Control Register TBCLR 0x03F7B bp 7 6 5 4 3 2 1 0 Bit name TM6BC7 TM6BC6 TM6BC5 TM6BC4 TM6BC3 TM6BC2 TM6BC1 TM6BC0 At reset 0 0 0 0 0 0 0 0 Access R R ...

Page 352: ...tarting operation of the timer 6 and the time base timer Timer 6 Enable Register TM6BEN 0x03F7C bp 7 6 5 4 3 2 1 0 Bit name TBEN TM6EN At reset 0 0 0 0 0 0 0 0 Access R R R R R R R W R W bp Bit name Description 7 to 2 Always read as 0 1 TBEN Time base timer operation control 0 Stop 1 Start 0 TM6EN Timer 6 operation control 0 Stop 1 Start ...

Page 353: ...zation of TM6BC when TM6OC is written When TM6CLRS 0 PERI0IRQ1 is disabled When TM6CLRS 1 PERI0IRQ1 is enabled 6 to 4 TM6IR2 to 0 Interrupt cycle of time base timer select 000 Time base selection clock 1 27 001 Time base selection clock 1 28 010 Time base selection clock 1 29 011 Time base selection clock 1 210 100 Time base selection clock 1 212 101 Time base selection clock 1 213 110 Time base s...

Page 354: ... next count clock and the binary counter is cleared to restart counting up from 0x00 Table 10 3 1 shows selectable clock sources Table 10 3 1 Clock Source at Timer Operation Timer 6 When SCLK is used as the clock source the timer counts at falling edge of the count clock When other clock is used it counts rising edge of the count clock Clock source One count time At fHCLK 8 MHz At fHCLK 4 MHz At f...

Page 355: ...tten to the compare register during the TM6CLRS 1 the binary counter is not cleared 3 When the binary counter reaches the setting value of the compare register during the TM6CLRS 1 an inter rupt request is set at the next count clock 4 When an interrupt request is set the binary counter is cleared to 0x00 and restarts counting 5 Even if the binary counter reaches the setting value of the compare r...

Page 356: ... multiple times In this case the read value is count value 1 II When changing the timer setting clock selection function switching etc wait for 1 count clock after setting the TM6EN TBEN bit to 0 to stop the timer Then Restart the timer If the setting is switched during the timer operation the timer operation is not guaranteed When the binary counter reaches the setting value of the compare regist...

Page 357: ...e interrupt 3 Select the clock source TM6MD 0x03F7A bp3 1 TM6CK3 1 001 3 Set the TM6CK3 1 bits of the TM6MD register to select the clock source In this case SYSCLK is selected 4 Set the interrupt generation cycle TM6OC 0x03F79 0xF9 4 Set the interrupt generation cycle to the timer 6 compare register TM6OC At this time TM6BC is initialized to 0x00 5 Enable the interrupt request generation TM6MD 0x0...

Page 358: ...ion cycles on each clock source Table 10 4 1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle HCLK 27 1 fHCLK 16 µs 28 1 fHCLK 32 µs 29 1 fHCLK 64 µs 210 1 fHCLK 128 µs 212 1 fHCLK 512 µs 213 1 fHCLK 1024 µs 214 1 fHCLK 2048 µs 215 1 fHCLK 4096 µs SCLK 27 1 fSCLK 3 9 ms 28 x 1 fSCLK 7 8 ms 29 1 fSCLK 15 6 ms 210 1 fSCLK 31 3 ms 212 1 fSCLK 12...

Page 359: ...rrupt cycle elapsed the time base interrupt request PERI0DT2 of the peripheral function group 0 interrupt factor register PERI0DT is set to 1 Stop the timer when switching the count clock If the count clock is changed during counting the timer doesn t count correctly The timer can be initialized by writing an arbitrary value to the time base timer clear control register TBCLR 13 1 2 12 14 11 10 9 ...

Page 360: ...isable the interrupt 3 Select the interrupt generation cycle TM6MD 0x03F7A bp6 4 TM6IR2 0 101 3 Set the TM6IR2 0 bits of the TM6MD register to select the specified clock 1 213 as an interrupt generation cycle 4 Initialize the time base timer TBCLR 0x03F7B 0x00 4 Write an arbitrary value to the time base timer clear control register TBCLR to initialize the time base timer 5 Set the interrupt level ...

Page 361: ...XI Chapter 11 RTC Time Base Timer RTC TBT 11 ...

Page 362: ...quency of RTC TBT interrupt 1 Hz 2 Hz 4 Hz 8 Hz 16 Hz 32 Hz 64 Hz 128 Hz In the case of SCLK of 32 768 kHz Adjustment for the 1 Hz clock period When selecting 32 768 kHz clock Range Period of 128 sec 488 ppm to 488 ppm Period of 32 sec 1954 ppm to 1952 ppm Period of 8 sec 7813 ppm to 7805 ppm Period of 2 sec 31250 ppm to 31220 ppm Accuracy Period of 128 sec 0 48 ppm Period of 32 sec 1 92 ppm Perio...

Page 363: ...ontrol Register Symbol Address R W Register Name Page TBTCNT0 0x03EEA R W RTC TBT control register 0 XI 4 TBTCNT1 0x03EEB R W RTC TBT control register 1 XI 5 TBTR 0x03EEC R W RTC TBT register XI 6 TBTADJL 0x03EEE R W RTC TBT frequency adjustment register for lower bits XI 8 TBTADJH 0x03EEF R W RTC TBT frequency adjustment register for upper bits XI 8 ...

Page 364: ... 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 TBTCLKSEL Clock source select for RTC TBT 0 SOSCCLK 1 SRCCLK 6 5 ADJCNT1 0 Adjustment period select for RTC TBT 00 128 sec 01 32 sec 10 8 sec 11 2 sec 4 Always read as 0 3 TBTIRQEN Interrupt enable for RTC TBT 0 Disable 1 Enable 2 0 TBTIRQSEL 2 0 Interrupt cycle select for RTC TBT 000 128 Hz 001 64 Hz 010 32 Hz 011 16 Hz 100 8 H...

Page 365: ... TBTCLKOE TBTCLKOS3 0 At reset 0 0 0 0 0 0 0 0 Access R W R R R R W R W R W R W bp Bit name Description 7 TBTCLKOE Clock output enable for RTC TBT 0 Disable 1 Enable 6 4 Always read as 0 3 0 TBTCLKOS 3 0 Clock output select for RTC TBT 0000 256 Hz 0001 128 Hz 0010 64 Hz 0011 32 Hz 0100 16 Hz 0101 8 Hz 0110 4 Hz 0111 2 Hz 1000 1 Hz ...

Page 366: ... the indeterminate data during counting up may be read bp 7 6 5 4 3 2 1 0 Bit name T1HZ T2HZ T4HZ T8HZ T16HZ T32HZ T64HZ T128HZ At reset X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Description 7 T1HZ T1HZ output of RTC TBT 6 T2HZ T2HZ output of RTC TBT 5 T4HZ T4HZ output of RTC TBT 4 T8HZ T8HZ output of RTC TBT 3 T16HZ T16HZ output of RTC TBT 2 T32HZ T32HZ output of RTC TBT ...

Page 367: ...ncy Adjustment Rate Adjustment period 128 sec TBTADJ10 0 Hexadecimal Frequency adjustment rate ppm 10 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 1 1 1 0x3FF 487 80 0 1 1 1 1 1 1 1 1 1 0 0x3FE 487 33 0 1 1 1 1 1 1 1 1 0 1 0x3FD 486 85 0 0 0 0 0 0 0 0 1 0 0 0x004 1 91 0 0 0 0 0 0 0 0 0 1 1 0x003 1 43 0 0 0 0 0 0 0 0 0 1 0 0x002 0 95 0 0 0 0 0 0 0 0 0 0 1 0x001 0 48 0 0 0 0 0 0 0 0 0 0 0 0x000 0 1 1 1 1 1 1...

Page 368: ... by RTC TBT and therefore the calen dar calculation is affected by the frequency adjustment bp 7 6 5 4 3 2 1 0 Bit name TBTADJ7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 TBTADJ7 0 Frequency adjustment setting lower 8 bits bp 7 6 5 4 3 2 1 0 Bit name TBTADJ10 8 At reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W bp Bit name Description 7 3 Alway...

Page 369: ...HZ T16HZ T8HZ T4HZ and T2HZ bits of the TBTR register are used as RTC TBT inter rupt The interrupt request is generated at the rising edge of each output When writing data to the TBTR register it is cleared and T128HZ T64HZ T32HZ T16HZ T8HZ T4HZ T2HZ and T1HZ become 0 Figure 11 3 1 Output Waveform and clearing time of RTC TBT T256HZ T128HZ T64HZ T32HZ T16HZ TBTR Write request T8HZ T4HZ T2HZ T1HZ ...

Page 370: ...RI0LV1 0 bits to 00 Clear the corresponding interrupt request bit of PERI0DT register if it may have already been set Refer to Chapter 3 3 1 3 Maskable Interrupt Control Register Setup 3 Set output of RTC TBT interrupt TBTCNT0 Set the TBTIRQSEL2 0 bits of TBTCNT0 register to 000 4 Enable output of RTC TBT interrupt TBTCNT0 Set the TBTIRQEN bit of TBTCN0 register to 1 5 Enable RTC TBT interrupt PER...

Page 371: ...XII Chapter 12 Real Time Clock RTC 12 ...

Page 372: ...visible by 4 are set as leap years Two time Display mode 12 hour clock or 24 hour clock Periodic interrupt 1 2 second 1 second 1 minute 1 hour Alarm 0 interrupt Generated when specified date hour minute match Alarm 1 interrupt Generated when specified month day hour minute match Controls Alarm 0 interrupts Controls Alarm 1 interrupts Alarm 0 interrupt Alarm 1 interrupt Periodic interrupt Clock Cou...

Page 373: ...arm 1 interrupt control register XII 7 AL1IRQMI 0x03ED8 R W Alarm 1 minutes setting register XII 7 AL1IRQH 0x03ED9 R W Alarm 1 hours setting register XII 8 AL1IRQD 0x03EDA R W Alarm 1 day setting register XII 8 AL1IRQMO 0x03EDB R W Alarm 1 month setting register XII 9 RTCCIRQ 0x03ED2 R W Periodic interrupt control register XII 10 RTCSD 0x03EE0 R W Seconds setting register XII 11 RTCMID 0x03EE1 R W...

Page 374: ...hen CLKEN is 0 HDMD and CLKEN must not be set at the same time bp 7 6 5 4 3 2 1 0 Bit name HDMD CLKEN At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R R bp Bit name Description 7 to 4 Always read as 0 3 HDMD Display mode select 0 24 hour display mode 1 12 hour display mode 2 CLKEN RTC operation control 0 Stop 1 Start 1 to 0 Always read as 0 ...

Page 375: ...Alarm 0 interrupt control 0 Disabled 1 Enabled 5 to 3 Always read as 0 2 AL0IRQWEN Alarm 0 Date comparator enable control 0 Disable 1 Enable 1 AL0IRQHEN Alarm 0 Hour comparator enable control 0 Disable 1 Enable 0 AL0IRQMIEN Alarm 0 Minute comparator enable control 0 Disable 1 Enable bp 7 6 5 4 3 2 1 0 Bit name AL0IRQMI6 0 At reset 0 0 0 0 0 0 0 0 Access R R W R W R W R W R W R W R W bp Bit name De...

Page 376: ... as 0 6 AL0IRQH6 Alarm 0 AM PM setting 0 AM 1 PM This bit must be set in 12 hour clock mode In 24 hour clock mode this bit must be set to 0 5 to 0 AL0IRQH5 0 Alarm 0 Hour setting 24 hour clock mode Set a value within the range of 00 to 23 using the BCD format In 12 hour clock Set a value within the range of 00 to 11 using the BCD format The value which doesn t exist must not be set bp 7 6 5 4 3 2 ...

Page 377: ...d 1 Enabled 5 Always read as 0 4 AL1IRQMOEN Alarm 1 Month comparator enable control 0 Disable 1 Enable 3 AL1IRQDEN Alarm 1 Day comparator enable control 0 Disable 1 Enable 2 Always read as 0 1 AL1IRQHEN Alarm 1 Hour comparator enable control 0 Disable 1 Enable 0 AL1IRQMIEN Alarm 1 Minute comparator enable control 0 Disable 1 Enable bp 7 6 5 4 3 2 1 0 Bit name AL1IRQMI6 0 At reset 0 0 0 0 0 0 0 0 A...

Page 378: ...When 24 hour clock mode this bit must be set to 0 5 to 0 AL1IRQH5 0 Alarm 1 Hour setting 24 hour clock mode Set a value within the range of 00 to 23 using the BCD format In 12 hour clock Set a value within the range of 00 to 11 using the BCD format The value which doesn t exist must not be set bp 7 6 5 4 3 2 1 0 Bit name AL1IRQD5 0 At reset 0 0 0 0 0 0 0 0 Access R R R W R W R W R W R W R W bp Bit...

Page 379: ...D and AL1IRQW RTCAL1IRQ AL1IRQMI AL1IRQH AL1IRQD and AL1IRQW must be set when RTCAL1IRQ AL1IRQSET is 0 bp 7 6 5 4 3 2 1 0 Bit name AL1IRQMO4 0 At reset 0 0 0 0 0 0 0 1 Access R R R R W R W R W R W R W bp Bit name Description 7 to 5 Always read as 0 4 to 0 AL1IRQMO4 0 Alarm 1 Month setting Set a value within the range of 01 to 12 using the BCD format The value which doesn t exist must not be set ...

Page 380: ...ame CIRQHEN CIRQMIEN CIRQSEN CIRQS05EN At reset 0 0 0 0 0 0 0 0 Access R R R R W R W R W R W R bp Bit name Description 7 to 5 Always read as 0 4 CIRQHEN Periodic interrupt control The periodic interrupt is generated every hour 0 Disable 1 Enable 3 CIRQMIEN Periodic interrupt control The periodic interrupt is generated every minute 0 Disable 1 Enable 2 CIRQSEN Periodic interrupt control The periodi...

Page 381: ...econd setting Set a value within the range of 00 to 59 using the BCD format The value which doesn t exist must not be set The value is incremented by one from 00 to 59 per second bp 7 6 5 4 3 2 1 0 Bit name MID6 0 At reset 0 0 0 0 0 0 0 0 Access R R W R W R W R W R W R W R W bp Bit name Description 7 Always read as 0 6 to 0 MID6 to 0 Minute setting Set a value within the range of 00 to 59 using th...

Page 382: ... within the range of 00 to 23 using the BCD format The value is incremented by one from 00 to 23 per hour In 12 hour clock Set a value within the range of 00 to 11 using the BCD format The value is incremented by one from 00 to 11 per hour The value which doesn t exist must not be set bp 7 6 5 4 3 2 1 0 Bit name WD2 0 At reset 0 0 0 0 0 0 0 0 Access R R R R R R W R W R W bp Bit name Description 7 ...

Page 383: ... 2 1 0 Bit name MOD4 0 At reset 0 0 0 0 0 0 0 1 Access R R R R W R W R W R W R W bp Bit name Description 7 to 5 Always read as 0 4 to 0 MOD4 to 0 Month setting Set a value within the range of 01 to 12 using the BCD format The value is incremented by one from 01 to 12 per day The value which doesn t exist must not be set bp 7 6 5 4 3 2 1 0 Bit name YD7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W ...

Page 384: ...atus Register RTC Status Register RTCSTR 0x03ED1 bp 7 6 5 4 3 2 1 0 Bit name LEAPFL At reset 0 0 0 0 0 0 0 1 Access R R R R R R R R bp Bit name Description 7 to 1 Always read as 0 0 LEAPFL Leap year flag 0 The RTCYD does not show a leap year 1 The RTCYD shows a leap year ...

Page 385: ...AL0IRQ AL0IRQWEN is 0 AL0IRQW is not compared with the calendar calculator When the RTCAL0IRQ AL0IRQHEN is 0 AL0IRQH is not compared with the calendar calculator When the RTCAL0IRQ AL0IRQMIEN is 0 AL0IRQMI is not compared with the calendar calculator Alarm 1 interrupt Alarm 1 interrupt occurs when the condition which is defined with the AL1IRQMI the AL1IRQH the AL1IRQD and the AL1IRQMO matches the...

Page 386: ...c interrupt In the interrupt handler of 1 second periodic interrupt read the calendar information Figure 12 3 1 Clock Data Reading Procedure 1 2 Reading the calendar information several times Reading the calendar information several times until confirming the calendar information is stable Figure 12 3 2 Clock Data Reading Procedure 2 Start A periodic interrupt with a cycle of a second is generated...

Page 387: ...2010 using the following registers RTCYD Set it to 0x10 RTCMOD Set it to 0x04 RTCDD Set it to 0x01 RTCWD Set it to 0x04 RTCHD Set it to 0x01 RTCMID Set it to 0x01 RTCSD Set it to 0x00 5 Periodic interrupt enabled RTCCIRQ Set the CIRQMIEN bit to 1 6 All maskable interrupts disabled PSW Set the MIE bit to 0 7 Interrupt level setting PERI0ICR Set the PERI0LV1 0 bits to 00 Clear the corresponding inte...

Page 388: ...d RTCAL0IRQ Set the AL0IRQSET bit to 1 6 Alarm detection enabled RTCAL0IRQ Set the AL0IRQWEN AL0IRQHEN and AL0IRQMIEN bits to 1 7 Alarm time setting Set the alarm time to 10 23 Saturday using the fol lowing registers AL0IRQW Set it to 0x6 AL0IRQH Set it to 0x10 AL0IRQMI Set it to 0x23 8 All maskable interrupts disabled PSW Set the IE bit to 0 9 Interrupt level setting PERI0ICR Set the PERI0LV1 0 b...

Page 389: ...XIII Chapter 13 Serial Interface 13 ...

Page 390: ...up B is not be allowed SCIF0 SCIF1 SCIF2 SCIF3 Clock Synchronous UART Full duplex Multi master IIC SCIF0 SCIF1 SCIF2 SCIF3 Pin group A B A B A B A B Clock synchronous Data I O pin SBO0A P65 SBO0B P36 SBO1A P30 SBO1B P46 SBO2A P42 SBO2B P23 SBO3A P04 SBO3B P52 Data input pin SBI0A P64 SBI0B P35 SBI1A P26 SBI1B P45 SBI2A P41 SBI2B P22 SBI3A P06 SBI3B P51 Clock I O pin SBT0A P66 SBT0B P37 SBT1A P31 S...

Page 391: ...TM count clock HCLK 2a a 0 1 2 3 4 5 6 7 8 SCLK 2b b 0 1 2 3 4 5 6 7 8 SYSCLK 2c c 0 1 2 3 4 5 6 First transfer bit MSB first or LSB first Clock polarity phase selection 2 3 4 wire communication Consecutive communication Interrupt SCnTICR SCIF0 SCIF1 Transfer clock Generated by dividing BRTMn output clock by 8 or 16 Duty of BRTM output clock 1 1 or 1 N BRTM count clock HCLK 2a a 0 1 2 3 4 5 6 7 8 ...

Page 392: ...TMn output clock by 8 Duty of BRTM output clock 1 1 or 1 N BRTM count clock HCLK 2a a 0 1 2 3 4 5 6 7 8 SCLK 2b b 0 1 2 3 4 5 6 7 8 SYSCLK 2c c 0 1 2 3 4 5 6 First transfer bit MSB first or LSB first Address format 7 bit address General call address Communication mode Standard mode 100 kHz High speed mode 400 kHz Interrupt SCnTICR SCnSICR ...

Page 393: ...RTM_S01_CK SCnMD1 SCnIOM Reception buffer Comparator Prescaler BRTM_SCn_SCLK BRTM output clock SCnMD1 SCnMST SBOnA SBOnB S E L SC01SEL SCnSEL1 SCnMD1 SCnCKM SCnMD1 SCnDIV SCnMD2 SCnFM1 0 SCnMD2 SCnPM1 0 SCnMD2 SCnBRKE SCnMD3 SCnFDC1 0 Baud rate timer BRTM UART Break reception SCnMD2 SCnBRKF UART Frame error detection SCnSTR SCnFEF UART Parity error detection SCnSTR SCnPEK Clock Synchronous UART Ov...

Page 394: ...ction SCnIICSTR IIC3STRT IIC General call detection SCnIICSTR IIC3GCALL Clock Synchronous IIC Overrun error detection SCnSTR SCnORE SCnMD1 SCnSBOS SBOn SBIn SBInA SBInB S E L SC23SEL SCnSEL0 SBTn SBTnA SBTnB S E L SC23SEL SCnSEL2 S E L SBOnA SBOnB S E L SC23SEL SCnSEL1 SBTn SBTnA SBTnB S E L SC23SEL SCnSEL3 SCnMD1 SCnMST SCnMD2 SCnSBCSEN SCnMD2 SCnSBCSLV Reception shift register Transmission contr...

Page 395: ...0 R W SCIF1 Mode Register 0 XIII 11 SC1MD1 0x03E41 R W SCIF1 Mode Register 1 XIII 13 SC1MD2 0x03E42 R W SCIF1 Mode Register 2 XIII 15 SC1MD3 0x03E43 R W SCIF1 Mode Register 3 XIII 17 SC1STR 0x03E44 R SCIF1 Status Register XIII 19 RXBUF1 0x03E45 R SCIF1 Reception Data Buffer XIII 10 TXBUF1 0x03E46 R W SCIF1 Transmission Data Buffer XIII 10 SC01SEL 0x03F1C R W SCIF01 I O Pin Switching Control Regist...

Page 396: ...14 SC3MD2 0x03E62 R W SCIF3 Mode Register 2 XIII 16 SC3MD3 0x03E63 R W SCIF3 Mode Register 3 XIII 18 SC3AD 0x03E64 R W SCIF3 Address Setting Register XIII 22 SC3STR 0x03E66 R W SCIF3 Status Register XIII 20 SC3IICSTR 0x03E67 R W SCIF3 Status Register for IIC dedicated XIII 21 RXBUF3 0x03E68 R SCIF3 Reception Data Buffer XIII 10 TXBUF3 0x03E69 R W SCIF3 Transmission Data Buffer XIII 10 SC23SEL 0x03...

Page 397: ...RXD1B Setting other value is prohibited 3 0 SC0SEL3 0 SCIF0 pin group selection 0000 SBCS0A SBT0A SBO0A TXD0A SBI0A RXD0A 1111 SBCS0B SBT0B SBO0B TXD0B SBI0B RXD0B Setting other value is prohibited bp 7 6 5 4 3 2 1 0 Bit name SC3SEL3 SC3SEL2 SC3SEL1 SC3SEL0 SC2SEL3 SC2SEL2 SC2SEL1 SC2SEL0 Initial value 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 4 SC3SEL3 0 SCI...

Page 398: ...BUF3 bp 7 6 5 4 3 2 1 0 Bit name RXBUFn7 RXBUFn6 RXBUFn5 RXBUFn4 RXBUFn3 RXBUFn2 RXBUFn1 RXBUFn0 Initial value X X X X X X X X Access R R R R R R R R bp Bit name Description 7 0 RXBUFn7 0 Received data is stored bp 7 6 5 4 3 2 1 0 Bit name TXBUFn7 TXBUFn6 TXBUFn5 TXBUFn4 TXBUFn3 TXBUFn2 TXBUFn1 TXBUFn0 Initial value X X X X X X X X Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0...

Page 399: ...eserved Reserved Initial value 0 0 0 0 0 1 1 1 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 SCnCE1 Clock polarity selection 0 Initial value High 1 Initial value Low 6 Reserved Always set to 0 5 SCnCTM Communication mode selection 0 Single byte communication 1 Consecutive byte communication 4 SCnDIR Transfer bit selection 0 MSB first 1 LSB first 3 0 Reserved Always set 0111 ...

Page 400: ... R W bp Bit name Description 7 SCnCE1 Clock polarity selection 0 Initial value High 1 Initial value Low 6 SCnCTM Communication mode selection 0 Single byte communication 1 Consecutive byte communication 5 IIC3DEM Always set to 0 4 SCnDIR Transfer bit selection 0 MSB first 1 LSB first 3 IIC3STE Start condition selection Selectable only in IIC communication always set to 0 in Clock Synchronous commu...

Page 401: ...BTS SBTn function control 0 Disable 1 Enable Input or Output transfer clock 5 SCnSBIS SBIn function control 0 Disable 1 fixed input 1 Enable Serial data input 4 SCnSBOS SBOn function control 0 Disable 1 Enable Serial data output 3 SCnCKM BRTM output clock division control 0 Not divided 1 Divided 2 SCnMST Clock master salve selection 0 Clock slave 1 Clock master 1 SCnDIV Division ratio of BRTM outp...

Page 402: ...put or Output transfer clock 5 SCnSBIS Serial input control selection 0 Disable 1 fixed input 1 Enable Serial data input 4 SCnSBOS SBOn function selection 0 Disable 1 Enable Serial data output 3 SCnIFS Interrupt trigger selection Selectable only in Clock Synchronous communication and always set 0 in IIC communication 0 Communication completion interrupt 1 TXBUFn empty interrupt 2 SCnMST Clock mast...

Page 403: ...SCnPM1 0 UART parity bit selection At transmission 00 Add 0 parity 01 Add 1 parity 10 Add odd parity 11 Add even parity At reception 00 Check 0 parity 01 Check 1 parity 10 Check odd parity 11 Check even parity 3 SCnNPE UART Parity addition enable control 0 Enabled 1 Disabled 2 SCnIFS Interrupt trigger selection Selectable only in Clock Synchronous communication and always set 0 in UART communicati...

Page 404: ...ial reset control 0 Reset 1 Reset release 4 0 is always read out 3 SCnCKPH Clock phase selection Selectable only in Clock Synchronous communication always set 0 in IIC communication 0 Data transmission at leading edge data reception at trailing edge 1 Data reception at leading edge data transmission at trailing edge 2 SCnSBCSE N SBCSn function selection Selectable only in Clock Synchronous communi...

Page 405: ...trol in UART transmission 0 Reset 1 Reset release 4 SCnRSRN Always set to 0 in Clock Synchronous communication Serial reset control in UART reception 0 Reset 1 Reset release 3 SCnCKPH Clock phase selection Selectable only in Clock Synchronous communication Always set 0 in IIC communication 0 Data transmission at leading edge data reception at trailing edge 1 Data reception at leading edge data tra...

Page 406: ...eserved IIC3STPC IIC3TMD IIC3REX SCnCMD IIC3ACKS IIC3ACKO Initial value 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 6 Reserved Always set to 0 5 IIC3STPC IIC stop condition generation 0 None 1 Generate stop condition 4 IIC3TMD IIC communication mode 0 Standard mode 1 High speed mode 3 IIC3REX Selection of Transmission reception in master communication 0 Transmi...

Page 407: ...Data transmission state 0 IDLE 1 During transmission 6 SCnRBSY Data reception state 0 IDLE 1 During reception 5 SCnTEMP Transmission data buffer empty detection 0 Detected 1 Not detected 4 SCnREMP Reception data buffer empty detection 0 Detected 1 Not detected 3 SCnFEF UART frame error detection 0 Not detected 1 Detected 2 SCnPEK UART parity error detection 0 Not detected 1 Detected 1 SCnORE Overr...

Page 408: ...R R R R R R R W bp Bit name Description 7 SCnTBSY Data transmission state in Clock Synchronous communication 0 IDLE 1 During transmission 6 0 is always read out 5 SCnTEMP Transmission data buffer empty detection 0 detected 1 Not detected 4 SCnREMP Reception data buffer empty detection 0 detected 1 Not detected 3 1 0 is always read out 0 SCnORE Overrun error detection 0 Not detected 1 detected ...

Page 409: ...t name IIC3WRS IIC3ABT _LST IIC3ADD _ACC IIC3STRT IIC3BUS BSY Reserved IIC3GC ALL IIC3DATA _ERR Initial value 0 0 0 0 0 0 0 0 Access R R W R R R R R R W bp Bit name Description 7 IIC3WRS Transmission reception mode in slave communication 0 Reception mode 1 Transmission mode 6 IIC3ABT_LST Arbitration lost detection 0 Not detected 1 Detected 5 IIC3ADD_ACC Slave address match detection 0 Not detected...

Page 410: ... W R W R W bp 7 6 5 4 3 2 1 0 Bit name BRTM_S3_MD BRTM_S2_MD BRTM_S1_MD BRTM_S0_MD Initial value 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 0 is always read out 3 BRTM_S3_MD Duty mode of BRTM3 output clock 0 1 1 1 1 N 2 BRTM_S2_MD Duty mode of BRTM2 output clock 0 1 1 1 1 N 1 BRTM_S1_MD Duty mode of BRTM1 output clock 0 1 1 1 1 N 0 BRTM_S0_MD Duty mode of BRTM0 outp...

Page 411: ...EN BRTM_S2 _EN BRTM_S1 _EN BRTM_S0 _EN Initial value 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 0 is always read out 3 BRTM_S3_EN BRTM3 count operation 0 Disabled 1 Enabled 2 BRTM_S2_EN BRTM2 count operation 0 Disabled 1 Enabled 1 BRTM_S1_EN BRTM1 count operation 0 Disabled 1 Enabled 0 BRTM_S0_EN BRTM0 count operation 0 Disabled 1 Enabled ...

Page 412: ...me BRTM_ S3_CKSEL BRTM_ S2_CKSEL BRTM_ S1_CKSEL BRTM_ S0_CKSEL Initial value 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description 7 4 0 is always read out 3 BRTM_S3_CKSEL BRTM3 base clock 0 HCLK 1 SCLK 2 BRTM_S2_CKSEL BRTM2 base clock 0 HCLK 1 SCLK 1 BRTM_S1_CKSEL BRTM1 base clock 0 HCLK 1 SCLK 0 BRTM_S0_CKSEL BRTM0 base clock 0 HCLK 1 SCLK ...

Page 413: ...011 BRT1SCLK 8 0100 BRT1SCLK 16 0101 BRT1SCLK 32 0110 BRT1SCLK 64 0111 BRT1SCLK 128 1000 BRT1SCLK 256 1001 SYSCLK 1010 SYSCLK 2 1011 SYSCLK 4 1100 SYSCLK 8 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRT1SCLK is the clock selected with BRTM_S_CKSEL BRTM_S1_CKSEL 3 0 BRTM_ S0_CK3 0 BRTM0 count clock selection 0000 BRT0SCLK 0001 BRT0SCLK 2 0010 BRT0SCLK 4 0011 BRT0SCLK 8 0100 BRT0SCLK 16 0101 BRT0S...

Page 414: ...011 BRT3SCLK 8 0100 BRT3SCLK 16 0101 BRT3SCLK 32 0110 BRT3SCLK 64 0111 BRT3SCLK 128 1000 BRT3SCLK 256 1001 SYSCLK 1010 SYSCLK 2 1011 SYSCLK 4 1100 SYSCLK 8 1101 SYSCLK 16 1110 SYSCLK 32 1111 SYSCLK 64 BRT3SCLK is the clock selected with BRTM_S_CKSEL BRTM_S3_CKSEL 3 0 BRTM_ S2_CK3 0 BRTM2 count clock selection 0000 BRT2SCLK 0001 BRT2SCLK 2 0010 BRT2SCLK 4 0011 BRT2SCLK 8 0100 BRT2SCLK 16 0101 BRT2S...

Page 415: ...ter BRTM_S0_OC BRTM_S1_OC BRTM_S2_OC BRTM_S3_OC bp 7 6 5 4 3 2 1 0 Bit name BRTM_Sn _OC7 BRTM_Sn _OC6 BRTM_Sn _OC5 BRTM_Sn _OC4 BRTM_Sn _OC3 BRTM_Sn _OC2 BRTM_Sn _OC1 BRTM_Sn _OC0 Initial value x x x x x x x x Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 BRTM_ Sn_OC7 0 BRTMn compare register ...

Page 416: ...ronous by using SCIFn n 2 3 set SCnMD3 SCnCMD to 0 13 3 1 Form 2 wire Communication Data transmission or reception is executed with a clock pin SBTn and a data pin SBOn or SBIn SBOn can be used for data transmission and reception SBIn is used only for data reception 3 wire Communication Data transmission and reception are executed with 3 pins SBTn SBOn and SBIn SBOn and SBIn are used for data tran...

Page 417: ... and SCnMD1 SCnSBOS to 1 SCnIOM must be set to 0 2 To use the clock pin SBTn the following setting is required At master SCnMD1 SCnMST is 1 the communication clock outputs from SBTn At slave SCnMD1 SCnMST is 0 input the communication clock to SBTn 3 In 4 wire communication the following setting of the chip select pin SBCSn is required SCIFn n 0 1 Set SCnMD3 SCnSBCSEN to 1 and select the direction ...

Page 418: ...nerating Baud Rate Timer Output Clock BRTM_SCnCLK SCIFn has a dedicated Baud Rate Timer BRTMn Select a count clock for BRTMn with BRTM_S_CKSEL BRTM_S01_CK and BRTM_S23_CK When BRTM_S_EN BRTM_Sn_EN is set to 1 the binary counter of BRTMn BRTM_Sn_BC starts counting up When BRTM_Sn_BC becomes equal to BRTM_Sn_OC BRTM_Sn_BC is cleared at the next count clock and restarts counting up While the duty of ...

Page 419: ...y 1 N Count Clock HCLK 4 N 0x01 Figure 13 3 5 BRTMn Count Operation Duty 1 N Count Clock HCLK N 0x03 When the duty is 1 N the value of 0x00 must not be set to BRTM_Sn_OC In Clock Synchronous communication BRTM_SCnCLK with 1 N duty must not be used as a transfer clock when SCnMD1 SCnCKM is 0 8 h01 8 h00 8 h01 8 h00 8 h01 8 h00 8 h01 8 h00 8 h01 8 h00 8 h01 8 h00 HCLK SYSCLK BRTM_Sn_EN BRTN_Sn_BC BR...

Page 420: ...Leading edge and the inverted rising edge is Trailing edge Table 13 3 1 Clock Edge of Data Transmission and Reception Figure 13 3 6 and Figure 13 3 7 show the 3 wire communication waveform when SCnCKPH 0 Figure 13 3 6 3 wire Communication Transmission Reception Timing When SCnCKPH 0 and SCnCE1 0 SCnCE1 SCnCKPH SBTn status during non communication Clock edge in data transmission Clock edge in data ...

Page 421: ...BCSn was asserted In slave communication input a transfer clock to SBTn after the time of 0 5 transfer clock 0 5 T has elapsed since SBCSn was asserted The last bit data output hold time of transmission data is different depending on the value of SCnCKPH Refer to Figure 13 3 8 and Figure 13 3 9 Allow adequate 1 T time for the last bit of reception data to hold data Figure 13 3 8 4 wire Communicati...

Page 422: ...igure 13 3 9 4 wire Communication Transmission Reception Timing SCnCKPH 0 T 0 5 T 1 5 SCnCLK frequency SBTn SBIn reception timing SBOn SBCSn At master SBOn At slave At master output At slave input SBCSn SCnCE1 0 SBTn SCnCE1 1 Last bit data hold period 0 5T minimum value ...

Page 423: ...lave a transfer clock is not input to prevent abnormal operation caused by external noise while serial communication is not executed Transfer clock input is enabled after a wait time Twait of 3 5 transfer clocks has elapsed after a data is written to TXBUFn Reception Data Buffer RXBUFn and Reception Buffer Empty Flag SCnREMP RXBUFn is a buffer to store the received data The received data in the re...

Page 424: ...XBUFn before a communication completion interrupt SCnTBSY is held at 1 Reception BUSY Flag SCIF0 and SCIF1 When SCnMD1 SCnSBIS is 1 SCnSTR SCnRBSY is set to 1 by writing data to TXBUFn While SCnSTR SCnTEMP is 0 SCnSTR SCnRBSY is cleared to 0 by a communication complete interrupt If SCnTEMP is 1 by writing data to TXBUFn before a communication completion interrupt SCnRBSY is held at 1 Communication...

Page 425: ...ve communication When a setting timing is delayed a transfer clock is masked and a communication does not work properly Single byte Communication Mode When SCnMD0 SCnCTM is 0 single byte communication mode is selected In this mode the following blank is inserted 1 When writing the next data to TXBUFn by the time specified with inverted triangle sign in Figure 13 3 11 Figure 13 3 12 Figure 13 3 13 ...

Page 426: ...n with STANDBY mode in SDIF0 SCIF1 set SCnMD0 SCnCTM and SCnMD3 SCnCKPH to 0 If they are not set to 0 SCIFn does not work properly When the reception with STANDBY mode in SDIF2 SCIF3 set SCnMD0 SCnCTM and SCnMD2 SCnCKPH to 0 If they are not set to 0 SCIFn does not work properly A transfer clock can be input after a time of 3 5 transfer clocks has elapsed since the activa tion source with a data wr...

Page 427: ...nCKPH bit 0 T Communication completion interrupt Set data to TXBUFn SCnTBSY SBTn SBOn Twait 3 5T 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit Writing period to TXBUFn when consecutive communication mode T Communication completion interrupt Set data to TXBUFn Writing period to TXBUFn when consecutive communication mode Twait 3 5T SBTn SBOn SCnTBSY 1st Bit 2nd Bit 3rd Bit 4th Bit ...

Page 428: ...ation completion interrupt Set data to TXBUFn SCnRBSY Writing period to TXBUFn when consecutive communication mode SBOn SBIn SBTn 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit Twait 3 5T T Communication completion interrupt Set data to TXBUFn SCnRBSY Twait 3 5T Writing period to TXBUFn when consecutive communication mode SBOn SBIn SBTn 1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th ...

Page 429: ...e Initial setting before communication XIII 42 Data transmission reception 1 byte communication mode XIII 43 Data transmission 1 byte communication mode XIII 43 Data reception 1 byte communication mode XIII 44 Data transmission reception consecutive communication mode XIII 44 Data transmission consecutive communication mode XIII 45 Data reception consecutive communication mode XIII 45 ...

Page 430: ...r BRTMn are set 5 Mode register setting SCnMD0 SCnMD1 SCnMD2 SCnMD3 Set SCIFn operation mode 6 Pin setting Enable communication pins SCIFn n 0 1 SCnMD1 SCnSBOS SCnMD1 SCnSBIS SCnMD1 SCnSBTS SCnMD3 SCnSBCSEN SCIFn n 2 3 SCnMD1 SCnSBOS SCnMD1 SCnSBIS SCnMD1 SCnSBTS SCnMD2 SCnSBCSEN Set pins to be used for serial communication to 1 7 Pin setting Enable serial output PnMD Enable communication pins 8 C...

Page 431: ...ion data read from RXBUFn RXBUFn Read out the reception data from RXBUFn 5 Confirmation of overrun error SCIFn n 0 1 SCnSTR SCnORE SCnSTR SCnERE SCIFn n 2 3 SCnSTR SCnORE If SCnORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea sures such as data retransmission since reception data may be destroyed SCnERE is only for SCIFn n 0 1 6 Transmission re...

Page 432: ...Setting Register name Description 1 Empty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR1 SCnTEMP is 0 2 Data write to TXBUFn The first data transmission TXBUFn Set transmission data in TXBUFn 3 Empty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR SCnTEMP becomes 0 since communica tion starts 4 Data write to TXBUFn The second and subsequent data tr...

Page 433: ...smis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR1 SCnTEMP is 0 2 Data write to TXBUFn The first data transmission TXBUFn Set dummy data in TXBUFn 3 Empty confirmation of transmis sion buffer SCnSTR SCnTEMP Confirm that SCnSTR SCnTEMP becomes 0 since communi cation starts 4 Data write to TXBUFn The second and subsequent data transmission TXBUFn Set the next dummy data in TXBUFn 5 Wait for commun...

Page 434: ...mitted or received by using either TXDn or RXDn TXDn is used for both data transmission and reception RXDn is used for data reception only 2 wire UART full duplex UART Data are transmitted and received with 2 wire communication by using both TXDn and RXDn TXDn is used for data transmission and RXDn is used for data reception Be sure to set the data frame and parity bit on the transmission receptio...

Page 435: ... and SCnMD2 SCnPM1 0 Table 13 4 2 Parity Bit of UART Serial Interface Start bit 1 bit Character bit 7 to 8 bits Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1to 2 bits SCnMD2 Transmission Reception SCnNPE SCnPM1 SCnPM0 0 0 0 Fixed to 0 Confirm parity bit is 0 0 0 1 Fixed to 1 Confirm parity bit is 1 0 1 0 For the total number of 1 of character bit odd 0 even 1 Confirm the total number o...

Page 436: ...unication At data reception Set SCnMD1 SCnSBIS to 1 and SCnMD1 SCnSBOS to 0 At data transmission Set SCnMD1 SCnSBIS to 0 and SCnMD1 SCnSBOS to 1 When SCnMD1 SCnIOM is 1 data reception via SBOn is enabled 2 wire communication Set both SCnMD1 SCnSBIS and SCnMD1 SCnSBOS to 1 SCnIOM must be set to 0 In UART communication set SCnMD1 SCnSBTS and SCnMD3 SCnSBCSEN to 0 In time division 1 wire communicatio...

Page 437: ...TEMP is 0 If data is written to TXBUFn while SCnTEMP is 1 SCIFn does not work properly As in the Clock Synchronous communication a wait time Twait from a data write to TXBUFn to the first data transmission is the period of 3 5 transfer clocks A start bit is transmitted after 2 5 transfer clocks after a data is written to TXBUFn Reception Data Buffer RXBUFn and of Reception Buffer Empty Flag SCnREM...

Page 438: ...ll bits of the data frame is 0 is transmitted To send a normal data set SCnMD2 SCnBRKE to 0 Be sure to write data to SCnBRKE while both SCnSTR SCnTBSY and SCnSTR SCnTEMP are 0 Break Reception A break is detected with SCnMD2 SCnBRKF When the break is detected SCnBRKF is set to 1 at the event of SCnRIRQ SCnBRKF is updated every time SCnRICR occurs so read out SCnBRKF before the next data is received...

Page 439: ... Storage MSB first Figure 13 4 3 Transmission Data Storage LSB first Data Storage to RXBUFn In MSB first mode reception data are stored in RXBUFn in order from the upper bit For example when receiving 7 bit data each bit from A to G A is the first reception bit is stored in RXBUFn from bp7 to bp1 as shown in Figure 13 4 4 In LSB first mode reception data are stored in RXBUFn in order from the lowe...

Page 440: ... 13 4 6 Transmission Timing with Parity Bit Figure 13 4 7 Transmission Timing without Parity Bit Parity bit Stop bit Stop bit T TXD Transmission completion interrupt SCnTBSY Set data toTXBUFn Twait 2 5T Stop bit Stop bit T TXD pin Transmission completion interrupt SCnTBSY Set data to TXBUFn Twait 2 5T ...

Page 441: ... 8 Reception Timing with Parity Bit Figure 13 4 9 Reception Timing without Parity Bit Parity bit Stop bit Stop bit Start condition input T RXDn Reception completion interrupt SCnRBSY Twait 0 5T Stop bit Stop bit Start condition input T RXDn Reception completion interrupt SCnRBSY Twait 0 5T ...

Page 442: ...Refer to the chapter IO Port for setting general purpose ports 4 BRTMn setting BRTM_S_MD BRTM_S_CKSEL BRTM_S01_CK BRTM_S23_CK BRTM_Sn_OC While BRTMn is active set BRTM_S_EN BRTM_Sn_EN to 0 to stop counting Output clock cycle and duty for BRTMn are set 5 Mode register setting SCnMD0 SCnMD1 SCnMD2 SCnMD3 Set SCIFn operation mode 6 Pin setting 2 SCnMD1 SCnSBOS SCnMD1 SCnSBIS Set pins used for serial ...

Page 443: ...ep 5 if there is enough time to check it 4 Reception data read from RXBUFn RXBUFn Read out the reception data from RXBUFn 5 Confirmation of overrun error SCnSTR SCnORE SCnSTR SCnERE If SCnORE SCnERE is 1 it indicates an overrun error has occurred When an overrun error has occurred take mea sures such as data retransmission since reception data may be destroyed 6 Reception end Repeat these procedur...

Page 444: ...hich 7 bit slave addresses are sent following a start condition Figure 13 5 1 Communication Sequence in 7 bit Addressing Format Data from other IIC ACK NACK ACK Start condition Start condition Start condition Start condition Slave address Slave address Slave address Slave address Data Stop condition Data Stop condition Data Stop condition Data Stop condition ACK ACK Master transmission Master rece...

Page 445: ... condition detection interrupt SCnSICR occurs when s stop condition is detected SCnSIRQ doesn t occur when it is generated by the LSI Generating Start Restart Condition When SC3MD0 IIC3STE is 1 a restart condition is generated by setting an address data consisting of 7 bit slave address R W bit to TXBUFn A start condition is generated by writing a address data to TXBUFn regard less of the value of...

Page 446: ...tection Condition Busy Flag IIC3BUSBSY is set when a start condition is detected on the IIC bus and is cleared when a stop condition is detected It is possible to check that IIC communication is executed between devices on IIC bus ACK NACK Transmission and Detection When the LSI receive data select ACK NACK transmission with SCnMD3 IIC3ACKO When the LSI send data confirm that ACK NACK is received ...

Page 447: ... timing SCnTIRQ or SCnSIRQ Clear IIC3ABT_LST by program General Call Communication When a general call is detected SCnIICSTR IIC3ADD_ACC and SCnIICSTR IIC3GCALL are set and send ACK bit The value of SCnIICSTR IIC3GCALL is valid only when SCnTIRQ occurs in the slave address recep tion Operation of Transmission Data Buffer register TXBUFn and Transmission Data Buffer Empty Flag SCnTEMP TXBUFn is a b...

Page 448: ...period of the transfer clock is extended since the slave device keeps SCLn Low Figure 13 5 3 SCLn without Low Period Extension by Slave Device Standard Mode Figure 13 5 4 SCLn with Low Period Extension by Slave Device Standard Mode Transfer rate SCnCLK divided by 8 3 5 SCnCLK SCLn SCnCLK SDAn Transfer clock output from the LSI Transfer rate SCnCLK divided by 9 High period extension Low period exte...

Page 449: ...lave Device High speed Mode Set the rising time of SCLn to the period of up to 0 5 SCNCLK in Standard Mode or up to 1 SCnCLK in High speed Mode Transfer rate SCnCLK divided by 8 SCLn SCnCLK SDAn 2 SCnCLK Transfer clock output from the LSI Transfer rate SCnCLK divided by 9 High period extension Low period extension by slave Transfer clock output from the LSI SCLn SCnCLK SDAn 2 SCnCLK ...

Page 450: ...to TXBUFn 2 Transmit Address data slave address R W bit 3 Receive ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive ACK bit 7 Set SCnMD3 IIC3STPC in interrupt handler 8 Generate stop condition 1 2 8 ACK 1 2 8 Set data to TXBUFn Set IIC3STPC 1 2 3 4 5 6 8 7 Set data to TXBUFn ACK address data transmission 8 bits transmission SDAn SCLn SCnTIRQ IIC3BUSBSY ...

Page 451: ...ata slave address R W bit 3 Receive ACK bit 4 Set SCnMD3 IIC3REX to 1 and write dummy data to TXBUFn in interrupt handler 5 Receive data 6 Transmit NACK bit 7 Set SCnMD3 IIC3STPC in interrupt handler 8 Generate stop condition 1 2 8 ACK 1 2 8 NACK address data transmission 8 bits reception 1 2 3 4 5 6 8 7 SDAn SCLn SCnTIRQ IIC3BUSBSY Set data to TXBUFn Set IIC3STPC Set dummy data to TXBUFn ...

Page 452: ...e address data slave address R W bit 3 Transmit ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive ACK bit 7 Set data to TXBUFn in interrupt handler 8 Transmit data 1 2 8 ACK 1 2 8 IIC3BUSBSY IIC3STRT IIC3ADD_ACC 1 3 4 2 6 5 7 8 ACK address data reception 8 bit transmission Set data to TXBUFn Set data to TXBUFn SDAn SCLn SCnTIRQ ...

Page 453: ...ception 1 Detect start condition 2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set data to TXBUFn in interrupt handler 5 Transmit data 6 Receive NACK bit 7 Release SDAn and SCLn 1 2 8 ACK 1 2 8 Set data to TXBUFn 1 3 4 2 6 5 7 NACK address data reception 8 bits transmission IIC3BUSBSY IIC3STRT IIC3ADD_ACC SDAn SCLn SCnTIRQ ...

Page 454: ...2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set dummy data to TXBUFn in interrupt handler 5 Receive data 6 Transmit ACK bit 7 Set dummy data to TXBUFn in interrupt handler 8 Detect stop condition 1 2 8 ACK 1 2 8 1 3 4 2 6 5 7 8 Set dummy data to TXBUFn ACK address data reception 8 bit reception IIC3BUSBSY IIC3STRT IIC3ADD_ACC SDAn SCLn SCnTIRQ Set dummy data to TXBUFn ...

Page 455: ...2 Receive address data slave address R W bit 3 Transmit ACK bit 4 Set dummy data to TXBUFn in interrupt handler 5 Receive data 6 Transmit ACK bit 47 Set dummy data to TXBUFn in interrupt handler 8 Detect restart condition 1 2 8 ACK 1 2 8 1 3 4 2 6 5 7 8 Set dummy data to TXBUFn ACK address data reception 8 bits reception IIC3BUSBSY IIC3STRT IIC3ADD_ACC SDAn SCLn SCnTIRQ Set dummy data to TXBUFn ...

Page 456: ...rst SCnSBCSLV SCnDIR Be sure to set it to 0 1 As initial setting register changed at the time of serial reset is shown below Please change it if needed such as interrupt setting or port setting Master setting at slave address transmission SCnMD0 SCnCE1 SCnCTM IIC3DEM SCnMD1 SCnIOM SCnMST SCnSBTS SCnSBIS SCnSBOS SCnMD2 SCnIFS SCnCKPH SCnSBCSEN SCnMD3 IIC3STPC IIC3REX SCnCMD IIC3ACKS Other SCnMD0 SC...

Page 457: ...tial setting register changed at the time of serial reset is shown below Please change it if needed such as interrupt setting or port setting Master setting at slave address transmission SCnMD0 SCnCE1 SCnCTM IIC3DEM SCnMD1 SCnIOM SCnMST SCnSBTS SCnSBIS SCnSBOS SCnMD2 SCnIFS SCnCKPH SCnSBCSEN SCnMD3 IIC3STPC IIC3REX SCnCMD IIC3ACKS Other SCnMD0 SCnMD3 SCnAD register SCnMD0 IIC3STE SCnMD3 IIC3TMD SC...

Page 458: ...Chapter 13 Serial Interface XIII 70 IIC Communication ...

Page 459: ...XIV Chapter 14 DMA Controller 14 ...

Page 460: ...ess memory during DMA data transfer if the bus collision between DMA and CPU doesn t happen DMA has the following features Table 14 1 1 Function Data transmission unit 8 bit or 16 bit Maximum number of DMA transfer 2 10 1 DMA start trigger External interrupt including Key interrupt Internal interrupt and Soft ware trigger Transfer mode Single transfer or Burst transfer Emergency stop DMA transfer ...

Page 461: ... 2 interrupt Timer 1 interrupt Timer 3 interrupt Timer 4 interrupt Timer 5 interrupt Timer 7 interrupt Timer 7 input capture factor Timer 8 interrupt Timer 8 input capture factor Timer 9 interrupt Timer 9 input capture factor Serial interface 0 reception interrupt Serial interface 0 transmission interrupt Serial interface 0 buffer empty factor Serial interface 1 reception interrupt Serial interfac...

Page 462: ...l register0 upper side XIV 6 DMCTR1L 0x03E02 R W DMA control register1 lower side XIV 7 DMCTR1H 0x03E03 R DMA control register1 upper side XIV 8 DMSRCL 0x03E04 R W DMA source address register lower side XIV 9 DMSRCM 0x03E05 R W DMA source address register middle side XIV 9 DMSRCH 0x03E06 R W DMA source address register upper side XIV 9 DMDSTL 0x03E08 R W DMA destination address register lower side...

Page 463: ... Timer 2 interrupt 01100 Timer 3 interrupt 01101 Timer 4 interrupt 01110 Timer 5 interrupt 01111 Timer 7 interrupt 10000 Timer 7 input capture factor 10001 Timer 8 interrupt 10010 Timer 8 input capture factor 10011 Timer 9 interrupt 10100 Timer 9 input capture factor 10101 Serial interface 0 reception interrupt 10110 Serial interface 0 transmission interrupt 10111 Serial interface 0 buffer empty f...

Page 464: ...MTM DMDAM At reset 0 0 0 0 0 0 0 0 Access R R R W R R W R R W R bp Bit name Description 7 6 Always read as 0 5 DMUT Data transmission unit 0 8 bit 1 16 bit 4 Always read as 0 3 DMTM Transfer mode 0 Burst transfer 1 Single transfer 2 Always read as 0 1 DMDAM Destination Address increment control 0 Enable Incremented 1 Disable Fixed 0 Always read as 0 ...

Page 465: ...tion 7 1 Always read as 0 0 DMTEN DMA transfer enable control After the DMTEN is set DMA waits for the DMA start trigger to occur When the software trigger is selected in DMCTR0L DMBG4 0 DMA transfer starts immediately after the DMTEN is set to 1 When the last data is transferred the DMTEN is cleared to 0 by hardware Setting the DMTEN to 0 during DMA transfer makes the transfer finished which is c...

Page 466: ...MA Error detection When the DMA Error occurs the DMOVF is set to 1 The DMOVF is cleared to 0 by writing DMCTR1L DMTEN 0 Not Detect 1 Detect 3 1 Always read as 0 0 DMRQF DMA Busy monitor The DMRQF is set to 1 when the DMA start trigger occurs In the case of the single transfer the DMRQF is cleared to 0 at the end of single data transfer In the case of the burst transfer the DMRQF is cleared to 0 at...

Page 467: ...dress lower side bit 0 to 7 This register shows the address where the next data to be loaded is contained bp 7 6 5 4 3 2 1 0 Bit name DMSA15 8 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 DMSA15 8 Source address middle side bit 8 to 15 This register shows the address where the next data to be loaded is contained bp 7 6 5 4 3 2 1 0 Bit name DMSA16 At r...

Page 468: ...address lower side bit 0 to 7 This register shows the address where the next data from source address is stored bp 7 6 5 4 3 2 1 0 Bit name DMDA15 8 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Bit name Description 7 0 DMDA15 8 Destination address middle side bit 8 to 15 This register shows the address where the next data from source address is stored bp 7 6 5 4 3 2 1 0 Bit n...

Page 469: ...t name DMCT7 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp 15 14 13 12 11 10 9 8 Bit name DMCT9 8 At reset 0 0 0 0 0 0 0 0 Access R R R R R R R W R W bp Bit name Description 15 10 Always read as 0 9 0 DMCT9 0 Number of DMA transfer This value is decremented when each transfer is finished 0x000 Prohibited 0x001 1 time 0x002 2 times 0x3FF 210 1 times transfers maximum ...

Page 470: ...ngle data from Source Address and before the DMCTR1L DMTEN is set to 1 by software for example the period B in the Figure 14 3 1 DMA AddReq interrupt occurs If the DMA start trigger happens during the time after the DMA start trigger occurs and before DMA reads the data not limited to the last single data from Source Address for example the period A in the Figure 14 3 1 DMA Error interrupt occurs ...

Page 471: ...ress and before the DMCTR1L DMTEN is set to 1 by software for example the period B in the Figure 14 3 2 DMA AddReq interrupt occurs If the DMA start trigger happens during the time after the DMA start trigger occurs and before DMA reads the last data from Source Address for example the period A in the Figure 14 3 2 DMA Error interrupt occurs Figure 14 3 2 Example of Burst Transfer Read Write DMA s...

Page 472: ...Chapter 14 DMA Controller XIV 14 DMA Data Transfer ...

Page 473: ...XV Chapter 15 Buzzer 15 ...

Page 474: ...14 or SCLK by 1 23 to 1 24 Figure 15 1 1 Buzzer Block Diagram BUZCTR BUZS2 0 BUZCTR BUZS2 0 BUZCTR BUZOE Output Control Clock Divider BUZCTR BUZOE Reset R MUX HCLK SCLK Count Clear Controller Buzzer Output BUZA BUZB Inverted Buzzer Output NBUZA NBUZB fHCLK 214 fHCLK 213 fHCLK 212 fHCLK 211 fHCLK 210 fHCLK 29 fSCLK 24 fSCLK 23 ...

Page 475: ...ers Table 15 2 1 Buzzer Control Registers Symbol Address R W Register name Page BUZCTR 0x03F7F R W Buzzer Control Register XV 4 P0DIR 0x03F30 R W Port 0 direction control register VII 12 P3DIR 0x03F33 R W Port 3 direction control register VII 13 BUZCNT 0x03F5F R W Buzzer output Buzzer output terminal control register VII 32 ...

Page 476: ...evel signal is output from BUZ NBUZ bp 7 6 5 4 3 2 1 0 Bit name BUZOE BUZS2 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R R R R bp Bit name Description 7 BUZOE Buzzer output selection 0 Buzzer output disable 1 Buzzer output enable 6 4 BUZS2 0 Buzzer output frequency selection 000 fHCLK 214 001 fHCLK 213 010 fHCLK 212 011 fHCLK 211 100 fHCLK 210 101 fHCLK 29 110 fSCLK 24 111 fSCLK 23 3 0 Alwa...

Page 477: ... 3 1 Buzzer Output Frequency Buzzer Output Pin Buzzer output pin and the polarity of it is decided with BUZCNT Refer to BUZCNT in 7 2 14 Buzzer output Buzzer output pin control Register for more information fHCLK fSCLK BUZS2 BUZS1 BUZSO Buzzer output frequency 10 MHz 0 0 0 0 61 kHz 10 MHz 0 0 1 1 22 kHz 4 MHz 0 1 0 0 98 kHz 4 MHz 0 1 1 1 95 kHz 2 MHz 1 0 0 1 95 kHz 2 MHz 1 0 1 3 91 kHz 32 kHz 1 1 ...

Page 478: ...et the BUZCTR BUZS to 010 2 Set the buzzer output pin BUZCNT P0OUT P0DIR Select the P02 as the buzzer output pin by Setting the BUZCNT BUZEN to 1 Setting the BUZCNT BUZSEL to 1 Select the output direction and the output data of 1 at P02 Set the P0OUT P0OUT2 to 0 Set the P0DIR P0DIR2 to 1 3 Enable buzzer output BUZCTR Set the BUZCTR BUZOE to 1 4 Disable buzzer output BUZCTR Set the BUZCTR BUZOE to ...

Page 479: ...XVI Chapter 16 A D Converter ADC 16 ...

Page 480: ...ons Table 16 1 1 ADC Functions This function can not be used in STOP HALT mode Do not execute mode switching as follows Normal operation state NORMAL to Low speed operation state SLOW Low speed operation state SLOW to Idle state IDLE to Normal operation state NOR MAL If the above mode switching is executed the result of A D conversion can not be guaranteed To realize a low power consumption it is ...

Page 481: ...REFP ANBUF10 ANBUF11 ANBUF12 ANBUF13 ANBUF14 ANBUF15 ANBUF16 ANBUF17 ANST MUX 1 18 12 bits A D comparator ANCTR1 ANCTR2 ANBUF1 0 7 ANCK0 ANCK1 ANCK2 ANSH0 ANSH1 ANCTR0 0 7 0 7 0 7 ANSTSEL1 1 6 1 2 ADIRQ ANLADE MUX ANSTSEL0 IRQ0 timer 7 interrupt control SCLK SYSCLK 8 SYSCLK 16 SYSCLK 6 SYSCLK 12 A D conversion data lower 4 bits ANBUF06 ANBUF07 ANBUF0 0 7 ANBUF04 ANBUF05 AN0 AN1 AN2 AN3 AN4 AN5 AN6...

Page 482: ...s that control the ADC Table 16 2 1 ADC Control Registers R W Readable Writable R Read only Symbol Address R W Register name Page ANCTR0 0x03F60 R W A D control register 0 XVI 5 ANCTR1 0x03F61 R W A D control register 1 XVI 6 ANCTR2 0x03F62 R W A D control register 2 XVI 6 ANBUF0 0x03F64 R ADC data storage buffer 0 XVI 7 ANBUF1 0x03F65 R ADC data storage buffer 1 XVI 7 ANEN0 0x03F5C R W Analog inp...

Page 483: ...W R W R W R W R W R W R R bp Bit name Description 7 6 ANSH1 0 Sample hold time 00 TADCLK 2 01 TADCLK 6 10 TADCLK 18 11 Prohibited 5 3 ANCK2 0 A D conversion clock ADCLK 000 SYSCLK 2 001 SYSCLK 3 010 SYSCLK 4 011 SYSCLK 6 100 SYSCLK 8 101 SYSCLK 12 110 SYSCLK 16 111 SCLK as 750 ns TADCLK 100 µs 2 ANLADE A D resistor ladder control 0 A D resistor ladder OFF 1 A D resistor ladder ON 1 0 Always read a...

Page 484: ...1 AN1 pin 010 AN2 pin 011 AN3 pin 100 AN4 pin 101 AN5 pin 110 AN6 pin 111 AN7 pin bp 7 6 5 4 3 2 1 0 Bit name ANST ANSTSEL1 0 At reset 0 0 0 0 0 0 0 0 Access R W R W R W R R R R R bp Bit name Description 7 ANST A D conversion status 0 Finish Stop 1 Start Converting 6 5 ANSTSEL1 0 A D conversion starting factor selection 00 Setting ANST bit to 1 01 External interrupt 0 or setting ANST bit to 1 10 T...

Page 485: ... A D conversion ADC Data Storage Buffer 1 ANBUF1 0x03F65 This register stores upper 8 bits after A D conversion bp 7 6 5 4 3 2 1 0 Bit name ANBUF07 ANBUF06 ANBUF05 ANBUF04 At reset X X X X 0 0 0 0 Access R R R R R R R R bp 7 6 5 4 3 2 1 0 Bit name ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 At reset X X X X X X X X Access R R R R R R R R ...

Page 486: ...NCTR0 ANSH1 0 Select the appropriate value based on the analog impedance The steps of 2 to 4 can be performed in random order The steps of 3 and 4 can be operated simultaneously 5 Set the A D resistor ladder Set the ANCTR0 ANLADE to 1 to apply current to the resistor ladder so that ADC will be in standby condi tion 6 Select the ADC activation factor then start A D conversion Set the ANCTR2 ANST to...

Page 487: ...2 ANSTSEL1 0 to 00 before setting ANCTR2 ANST If the data of ANCTR0 or ANCTR1 is changed during A D conversion the operation and the result of A D conversion cannot be guaranteed Set the ANCTR ANLADE to 0 to turn the A D resistor ladder off before changing the data of ANCTR0 or ANCTR1 Figure 16 3 1 Operation of A D conversion sample hold time at TADCLK 2 Before reading out the value of the A D con...

Page 488: ...nversion depends on the external circuit so set the appropriate value based on the analog input impedance Table 16 3 2 Sample Hold Time of A D Conversion and A D Conversion Time ANCK2 0 A D conversion clock A D conversion cycle TADCLK fHCLK 10 MHz fSCLK 32 768 kHz 000 SYSCLK 2 400 ns Setting is prohibited 61 035 µs 001 SYSCLK 3 600 ns Setting is prohibited 91 552 µs 010 SYSCLK 4 800 ns 122 070 µs ...

Page 489: ...r 7 interrupt or A D conversion interrupt In addition the A D conversion is started by setting the ANCTR2 ANST to 1 When External Interrupt 0 is selected as the A D conversion starting factor the valid edge should be assigned by IRQ0ICR REDG0 The interrupt valid edge need to be assigned before selecting the interrupt 0 factor for A D conversion starting factor A D Conversion Starting Setup The sta...

Page 490: ...rsion is restarted by changing the setting after the A D conversion set the ANCTR0 ANLADE to 0 to change the setup after stopping an analog circuit Note that operation is not guaranteed if the procedures above are not properly conducted After setting the ANCTR0 ANLADE to 1 and waiting for 12 conversion clocks start A D con version Analog input pin setting Analog pin function selection ANEN0 ANEN0 ...

Page 491: ...olt age pins VREFP which is positioned close to VSS pins Figure 16 3 3 ADC Recommended Example 1 Figure 16 3 4 ADC Recommended Example 2 During the A D conversion if the output level of LSI is changed or the additional peripheral circuits are switched to ON OFF the ADC may operate incorrectly as the analog control ter minals cannot be fixed At circuit board evaluation confirm the waveform of analo...

Page 492: ...ternal Capacitor When ROUT is large the input load will essentially comprise only RAD CAD and CIO by providing a large capac itance 1000 pF to 1 µF outside It is also recommended that a large capacitance is added to outside as the protection against noise for the analog signal In this case ADC may not be possible to follow the analog signal with the large differential coefficient by an external ca...

Page 493: ...XVII Chapter 17 LCD 17 ...

Page 494: ... VLC3 LCD Reference Voltage Circuit REFVOL 0 05 V increments within a range of 0 9 V to 1 8 V LCD Voltage Booster Circuit BSTVOL Boosts reference voltage input by 2 3 times Clock Source for LCD Display LCDCLKS SCLK HCLK 24 HCLK 25 HCLK 26 HCLK 27 HCLK 28 LCD Display Clock LCDCLK LCDCLKS 23 LCDCLKS 24 LCDCLKS 25 LCDCLKS 26 LCDCLKS 27 LCD CLKS 28 LCDCLKS 29 LCDCLKS 210 LCDCLKS 211 LCDCLKS 212 Clock ...

Page 495: ...V2 0 LCDMD0 LCUPCKS2 0 LCDMD4 LCUPMD SEG42 SEG0 SEG1 COM0 COM1 COM7 V SS C1 C2 V LC1 V LC2 V LC3 3 HCLK SCLK LCDATA0 LCDATA1 LCDATA42 8 8 8 LCDMD1 LCVREN LDCMD1 LCVRO4 0 8 LCDMD3 LCCK3 0 LCDMD3 LCCKS2 0 3 MUX MUX MUX Segment driver Common driver Segment output latch Circuit to control display timings LCD clock dividing circuit Booster circuit Reference power supply circuit Booster clock control ci...

Page 496: ...VII 7 LCDMD3 0x03E83 R W LCD mode control register 3 XVII 8 LCDMD4 0x03ECE R W LCD mode control register 4 XVII 8 LCCTR0 0x03E86 R W LCD output control register 0 XVII 9 LCCTR1 0x03E87 R W LCD output control register 1 XVII 10 LCCTR2 0x03E88 R W LCD output control register 2 XVII 11 LCCTR3 0x03E89 R W LCD output control register 3 XVII 12 LCCTR4 0x03E8A R W LCD output control register 4 XVII 13 LC...

Page 497: ...Access R W R W R W R W R W R W R W R W bp Bit name Description 7 LCUPEN BSTVOL enable control 0 stop 1 start 6 Reserved Must be set to 0 5 3 LCUPCKDIV2 0 LCUPCK selection 000 LCUPCKS 1 8 001 LCUPCKS 1 16 010 LCUPCKS 1 32 011 LCUPCKS 1 64 100 LCUPCKS 1 128 110 111 Setting prohibited 2 0 LCUPCKS2 0 LCUPCKS selection 000 SCLK 001 HCLK 24 010 HCLK 25 011 HCLK 26 100 HCLK 27 101 HCLK 28 110 111 Setting...

Page 498: ...Bit name LCVREN LCVRO4 0 At reset 0 0 0 0 0 0 0 0 Access R W R R R W R W R W R W R W bp Bit name Description 7 LCVREN REFVOL enable control 0 stop 1 start 6 5 Always read as 0 4 0 LCVRO4 0 Output voltage of REFVOL Incremented by 0 05 V 00000 0 9 V 00001 0 95 V 10010 1 8 V 10011 11111 Setting prohibited ...

Page 499: ... W R W R W R W R W R W R W bp Bit name Description 7 LCEN LCD display driver control 0 Stop 1 Start 6 to 5 LCMOD1 0 LCD display mode 00 Normal 01 All LCD on 10 All LCD off 11 Setting prohibited 4 LCMODS Selects a display waveform 0 Line reverse 1 Frame reverse 3 Reserved Must be set to 0 2 0 LCDTY2 0 LCD display duty 000 1 1 Static 001 1 2 010 1 3 011 1 4 100 1 5 101 1 6 110 1 7 111 1 8 ...

Page 500: ...KS 27 0101 LCDCLKS 28 0110 LCDCLKS 29 0111 LCDCLKS 210 1000 LCDCLKS 211 1001 LCDCLKS 212 1010 1111 Setting prohibited 2 0 LCCKS2 0 LCDCLKS selection 000 SCLK Low speed clock 001 HCLK High speed clock 24 010 HCLK High speed clock 25 011 HCLK High speed clock 26 100 HCLK High speed clock 27 101 HCLK High speed clock 28 110 111 Setting prohibited bp 7 6 5 4 3 2 1 0 Bit name Reserved LCUPMD At reset 0...

Page 501: ...0 selection 0 P70 1 COM7 SEG3 SEG3 P64 selection 0 P64 1 SEG3 Must be set to 0 6 SEGSL2 COM6 SEG2 P71 selection 0 P71 1 COM6 SEG2 SEG2 P65 selection 0 P65 1 SEG2 5 SEGSL1 COM5 SEG1 P72 selection 0 P72 1 COM5 SEG1 SEG1 P66 selection 0 P66 1 SEG1 4 SEGSL0 COM4 SEG0 P73 selection 0 P73 1 COM4 SEG0 SEG0 P67 selection 0 P67 1 SEG0 3 COMSL3 COM3 P74 selection 0 P74 1 COM3 COM3 P70 selection 0 P70 1 COM3...

Page 502: ...10 SEG6 P55 selection 0 P55 1 SEG6 5 SEGSL9 SEG9 P62 selection 0 P62 1 SEG9 SEG9 P56 selection 0 P56 1 EG9 SEG5 P56 selection 0 P56 1 SEG5 4 SEGSL8 SEG8 P63 selection 0 P63 1 SEG8 SEG8 P57 selection 0 P57 1 SEG8 SEG4 P57 selection 0 P57 1 SEG4 3 SEGSL7 SEG7 P64 selection 0 P64 1 SEG7 SEG7 P60 selection 0 P60 1 SEG7 SEG3 P60 selection 0 P60 1 SEG3 2 SEGSL6 SEG6 P65 selection 0 P65 1 SEG6 SEG6 P61 s...

Page 503: ...18 SEG18 P41 selection 0 P41 1 SEG18 SEG10 P41 selection 0 P41 1 SEG10 5 SEGSL17 SEG17 P52 selection 0 P52 1 SEG17 SEG17 P42 selection 0 P42 1 SEG17 SEG9 P42 selection 0 P42 1 SEG9 4 SEGSL16 SEG16 P53 selection 0 P53 1 SEG16 SEG16 P43 selection 0 P43 1 SEG16 SEG8 P43 selection 0 P43 1 SEG8 3 SEGSL15 SEG15 P54 selection 0 P54 1 SEG15 SEG15 P44 selection 0 P44 1 SEG15 SEG7 P44 selection 0 P44 1 SEG7...

Page 504: ...1 selection 0 P31 1 SEG18 5 SEGSL25 SEG25 P42 selection 0 P42 1 SEG25 SEG25 P32 selection 0 P32 1 SEG25 SEG17 P32 selection 0 P32 1 SEG17 4 SEGSL24 SEG24 P43 selection 0 P43 1 SEG24 SEG24 P33 selection 0 P33 1 SEG24 SEG16 P33 selection 0 P33 1 SEG16 3 SEGSL23 SEG23 P44 selection 0 P44 1 SEG23 SEG23 P34 selection 0 P34 1 SEG23 SEG15 P34 selection 0 P34 1 SEG15 2 SEGSL22 SEG22 P45 selection 0 P45 1 ...

Page 505: ...EG35 P30 selection 0 P30 1 SEG35 Must be set to 0 Must be set to 0 6 SEGSL34 SEG34 P31 selection 0 P31 1 SEG34 5 SEGSL33 SEG33 P32 selection 0 P32 1 SEG33 4 SEGSL32 SEG32 P33 selection 0 P33 1 SEG32 3 SEGSL31 SEG31 P34 selection 0 P34 1 SEG31 2 SEGSL30 SEG30 P35 selection 0 P35 1 SEG30 SEG30 P20 selection 0 P20 1 SEG30 1 SEGSL29 SEG29 P36 selection 0 P36 1 SEG29 SEG29 P21 selection 0 P21 1 SEG29 0...

Page 506: ...R W R W R W R W bp Bit name Description MN101LR05D MN101LR04D MN101LR03D 7 Always read as 0 6 SEGSL42 SEG42 P20 selection 0 P20 1 SEG42 Must be set to 0 5 SEGSL41 SEG41 P21 selection 0 P21 1 SEG41 4 SEGSL40 SEG40 P22 selection 0 P22 1 SEG40 3 SEGSL39 SEG39 P23 selection 0 P23 1 SEG39 2 SEGSL38 SEG38 P24 selection 0 P24 1 SEG38 1 SEGSL37 SEG37 P25 selection 0 P25 1 SEG37 0 SEGSL36 SEG36 P26 selecti...

Page 507: ...L5 COMSL4 At reset 0 0 0 0 0 0 0 0 Access R R R R R W R W R W R W bp Bit name Description MN101LR05D MN101LR04D MN101LR03D 7 4 Always read as 0 3 COMSL7 SEG3 COM7 selection 0 SEG3 1 COM7 Must be set to 0 2 COMSL6 SEG2 COM6 selection 0 SEG2 1 COM6 1 COMSL5 SEG1 COM5 selection 0 SEG1 1 COM5 0 COMSL4 SEG0 COM4 selection 0 SEG0 1 COM4 ...

Page 508: ...TA11 0x3E9B SEG11 LCDATA12 0x3E9C SEG12 LCDATA13 0x3E9D SEG13 LCDATA14 0x3E9E SEG14 LCDATA15 0x3E9F SEG15 LCDATA16 0x3EA0 SEG16 LCDATA17 0x3EA1 SEG17 LCDATA18 0x3EA2 SEG18 LCDATA19 0x3EA3 SEG19 LCDATA20 0x3EA4 SEG20 LCDATA21 0x3EA5 SEG21 LCDATA22 0x3EA6 SEG22 LCDATA23 0x3EA7 SEG23 LCDATA24 0x3EA8 SEG24 LCDATA25 0x3EA9 SEG25 LCDATA26 0x3EAA SEG26 LCDATA27 0x3EAB SEG27 LCDATA28 0x3EAC SEG28 LCDATA29...

Page 509: ...sed when the LSI is in STOP mode Before transiting to STOP mode the following procedures must be executed 1 Set the LCDMD2 LCUPEN to 1 and deactivate LCDDRV 2 When BSTVOL is activated set LCDMD0 LCUPEN to 0 After deactivating BSTVOL the voltage level of VLC1 is VDD30 3 When REFVOL is activated set LCDMD1 LCVREN to 0 After LSI reset VLC1 is in high impedance until the LDCDMD0 LCUPEN is set to 1 Whe...

Page 510: ...e VLC2 VLC3 from the short circuit pin of VLC2 and VLC3 pins 2 times the reference voltage VLC2 VLC3 is output from VLC1 pin Insert a capacitor at VLC1 VSS and C1 C2 pins In 2 or 3 times boosting the condition of 1 3 VDD30 VLC3 1 2 V must be ensured In 2 times boosting the condition of 1 2 VDD30 VLC2 VLC3 1 8 V must be ensured 17 3 3 Reference Voltage Circuit REFVOL This LSI has a built in referen...

Page 511: ... with BSTVOL The reference voltage is supplied from outside of the LSI 2 or 3 times boosting Supply the reference voltage VLC3 to VLC3 2 times higher voltage of VLC3 is output from VLC2 3 times higher voltage of VLC3 is output from VLC1 1 2 or 3 2 times boosting 1 3 bias Supply the reference voltage VLC2 to VLC2 1 2 times lower voltage of VLC2 is output from VLC3 3 2 times higher voltage of VLC2 i...

Page 512: ...ive voltage the maximum voltage supplied to LCD panel Figure 17 3 1 Connection Examples of LCD Power Supply when using external voltage dividing resistor Pin Name Voltage Level Static 1 2 bias 1 3 bias VLC1 VLC1 VLCD VSS VLCD VSS VLCD VSS VLC2 VLC2 1 2VLCD VSS 2 3VLCD VSS VLC3 VLC3 VSS 1 3VLCD VSS VLC1 VLC2 VLC3 VSS VDD30 VLC1 VLC2 VLC3 VSS VDD30 a Static VDD30 VLCD b 1 2duty 1 2bias VDD30 VLCD R ...

Page 513: ...igure 17 3 1 power is consumed at resistors all the time Figure 17 3 2 is the method to stop the above power consumption Figure 17 3 2 Connection example for LCD power supply Port VLC1 VLC2 VLC3 VSS VDD30 R R R VSS VDD30 VDD30 input C C C ...

Page 514: ...VLC3 VSS Table 17 3 3 Voltage Level of VLC1 VLC2 VLC3 when BSTVOL is used When the brightness of LCD panel is not enough increase the frequency of LCUPCK with the LCDMD0 LCUPCKDIV2 0 and LCDMD0 LCUPCKS2 0 or generate LCD drive voltage outside the LSI Refer to 1 In the case of generating the drive voltage outside the LSI Pin Name Voltage Level 2 times boost 2 3 times boost Static 1 2 bias 1 3 bias ...

Page 515: ... level of VLC1 VLC2 VLC3 when BSTVOL REFVOL are used Figure 17 3 3 Connection example of LCD power supply when BSTVOL REFVOL are used When the brightness of LCD panel is not enough increase the frequency of LCUPCK with the LCDMD0 LCUPCKDIV2 0 and LCDMD0 LCUPCKS2 0 or generate LCD drive voltage outside the LSI Refer to 1 In the case of generating the drive voltage outside the LSI Pin Name Voltage L...

Page 516: ...table shows the relation between the typical input frequency SCLK 32 kHz and LCD clocks Table 17 3 5 Input Frequency and LCD Clock Static Clock source Clock Frame frequency Hz LCCKS2 0 LCCK3 0 Frequency Hz Static 1 2 duty 1 4 duty 1 8 duty 000 SCLK selected 0000 4096 4096 2048 1024 512 0001 2048 2048 1024 512 256 0010 1024 1024 512 256 128 0011 512 512 256 128 64 0100 256 256 128 64 32 0101 128 12...

Page 517: ...VOL LCDMD1 0x03E81 bp7 LCVREN 1 LCDMD0 0x03E80 bp7 LCUPEN 1 2 Activate BSTVOL and REFVOL 3 SEG COM pins setting LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp3 0 COMSL3 0 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 3 Select SEG0 3 and COM0 3 pins 4 Select a LCDCLK LCDMD3 0x3E83 bp6 3 LCCK3 0 0111 bp2 0 LCCKS2 0 101 4 Select HCLK 218 as a display clock 5 Select a display duty LCDMD2 0x03E82 bp2 0 LCDTY2 0 011 5...

Page 518: ...3E97 0x03E90 0x03E91 0x03E92 0x03E93 0x03E94 0x03E95 0x03E96 0 0 0 0 bit3 bit2 bit1 bit0 COM3 COM2 COM1 COM0 SEG42 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 open A electrode B electrode LCDPANEL ON OFF 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 SEG6 SEG7 open open Undefined Undefined ON OFF OFF S selected voltage N non selected voltage VLCD LCD driving voltage COM COM0 always outputs the selected...

Page 519: ...D Display Examples XVII 27 Figure 17 4 1 LCD display example in static COM0 SEG4 data A electrode COM0 SEG4 COM0 SEG6 B electrode Frame period VLCD 0 VLCD VLCD VLCD 0 ON OFF 0 1 VLCD SEG6 data VLC1 VLC1 VLC1 VSS VSS VSS ...

Page 520: ...lay duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 000 2 Set the operation mode to static driving 3 Set a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 3 Select HCLK 215 as a display clock 4 Set Segment and common output pins LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp0 COMSL0 1 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 4 Select SEG0 7 and COM0 pins 5 Set the displa...

Page 521: ...ode LCDPANEL ON OFF 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 SEG4 SEG5 SEG6 SEG7 open open ON OFF OFF OFF OFF LCD clock Data COM SEG COM SEG VLC1 VLC2 VLC3 VSS VLCD 1 2VLCD 0 1 2VLCD VLCD LCD ON LCD OFF COM S SEG S COM N SEG S COM S SEG N COM N SEG N 1 0 VLC1 VLC2 VLC3 VSS Undefined Undefined S selected voltage N non selected voltage VLCD LCD driving voltage 0x03EBA 0x03E97 0x03E90 0x03E91 0x03E92 0x03E93 ...

Page 522: ...17 4 2 LCD display example in 1 2 duty COM1 COM0 SEG6 data COM1 SEG6 COM0 SEG6 VLC1 VLC1 VLC1 VLC2 VLC3 VLC2 VLC3 VLC2 VLC3 1 2VLCD 1 2VLCD VLCD 0 VLCD VLCD VLCD 1 2VLCD 1 2VLCD 0 VLCD VSS VSS VSS 0 1 A electrode B electrode Frame period ON OFF OFF OFF ...

Page 523: ... duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 001 2 Set the operation mode to 1 2 duty driving 3 Set a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 3 Select HCLK 215 as a display clock 4 Set Segment and common output pins LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp1 0 COMSL1 0 11 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 4 Select SEG0 7 and COM0 1 pins 5 Set the ...

Page 524: ...EG5 SEG4 SEG3 SEG2 SEG1 SEG0 open LCDPANEL LCD ON LCD OFF COM S SEG S COM N SEG S COM S SEG N COM N SEG N COM SEG COM SEG VLC1 VLC2 VLC3 VSS VLCD 1 3VLCD 0 1 3VLCD VLCD 1 0 VLC1 VLC2 VLC3 VSS A electrode B electrode ON OFF ON OFF OFF OFF OFF LCD clock Data Undefined Undefined S selected voltage N non selected voltage VLCD LCD driving voltage 0x03EBA 0x03E90 0x03E91 0x03E92 0x03E93 0x03E94 0x03E95 ...

Page 525: ...y example in 1 3 duty COM2 COM1 COM0 SEG5 data COM2 SEG5 COM1 SEG5 VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS 1 3VLCD 1 3VLCD VLCD 0 VLCD VLCD VLCD 1 3VLCD 1 3VLCD 0 VLCD 0 0 1 A electrode B electrode Frame period ON OFF OFF OFF OFF OFF ...

Page 526: ... LCD 2 Set a display duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 010 2 Set the operation mode to 1 3 duty driving 3 Set an LCD clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 3 Select HCLK 215 as an LCD clock source 4 Set Segment and common output pins LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp2 0 COMSL2 0 111 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E8E bp3 0 COMSL7 4 0000 4 Select SEG0 5 and ...

Page 527: ... SEG42 SEG3 SEG2 SEG1 SEG0 LCDPANEL LCD ON LCD OFF COM S SEG S COM N SEG S COM S SEG N COM N SEG N COM SEG COM SEG VLC1 VLC2 VLC3 VSS VLCD 1 3VLCD 0 1 3VLCD VLCD 1 0 VLC1 VLC2 VLC3 VSS A electrode B electrode ON OFF ON OFF OFF OFF OFF LCD clock Data Undefined Undefined S selected voltage N non selected voltage VLCD LCD driving voltage 0x03EBA 0x03E90 0x03E91 0x03E92 0x03E93 ...

Page 528: ...duty COM2 COM1 COM0 SEG3 data COM3 SEG3 COM1 SEG3 1 3VLCD 1 3VLCD VLCD 0 VLCD VLCD VLCD 1 3VLCD 1 3VLCD 0 VLCD COM3 VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS VLC1 VLC2 VLC3 VSS 1 1 0 1 A electrode B electrode Frame period OFF OFF OFF ON OFF OFF OFF OFF ...

Page 529: ...he LCD LCDMD2 0x03E82 bp7 LCEN 0 1 Stop the LCD 2 Set a display duty LCDMD2 0x03E82 bp2 0 LCDDTY2 0 011 2 Set the operation mode to 1 4 duty driving 3 Set a display clock LCDMD3 0x03E83 bp6 3 LCCK3 0 0100 bp2 0 LCCKS2 0 101 3 Select HCLK 215 as a display clock 4 Set Segment and common output pins LCCTR0 0x03E86 bp7 4 SEGSL3 0 1111 bp3 0 COMSL3 0 1111 LCCTR1 0x03E87 bp3 0 SEGSL7 4 1111 LCDSEL 0x03E...

Page 530: ...Chapter 17 LCD XVII 38 LCD Display Examples ...

Page 531: ...XVIII Chapter 18 ReRAM 18 ...

Page 532: ...ugger PanaX EX or a serial programmer Self programming ReRAM is programmed with the software embedded in the program area Function Description Memory size 64 KB Program endurance Program area 62 KB 1000 times Min Data area 2 KB 100 000 times Min Programming Voltage VDD30 1 8 V to 3 6 V Reading Voltage VDD30 1 1 V to 3 6 V Data retention duration 10 years ReRAM programming method Programmer writing...

Page 533: ...can not be deactivated by software Security Function Security Function is prevents all areas of the ReRAM reading or programming This function blocks interpolation and leak of the data in ReRAM Security Function is enabled or disabled with a key code 128 bit The key code cannot be changed once it is set Keep the key code in a safe place Without the key code ReRAM programming and rewriting cannot b...

Page 534: ...because of program troubles which may happen in an early phase of development program the data of ReRAM with Programmer writing method 0x03D82 0x03D87 0x04000 0x04100 0x04900 0x13FFF Address Access Disabled Registers for Programming Data Area 2 KB Program Area 61 75 KB Reserved Area 0x6F000 0x6FBFF Rewritable Area Program Area 256 B Access Disabled Address MAP FBEWER 0x4B 0x03D82 0x03D87 0x04000 0...

Page 535: ... during Programming When an interrupt occurs during the execution of a command library the processing of the command library is suspended and the interrupt process is executed After the interrupt process is finished the command library is resumed Start Rewriting End Rewriting Call Return Command Library Start Command Library End ReRAM Programming 2 Set the necessary parameters in the control regis...

Page 536: ... R W Rewriting enable register 0x4B Enable programming Others Disable programming WADDR_L WADDR_M WADDR_H 0x03D82 0x03D83 0x03D84 R W Rewrite address register Specify the address to be rewritten WBC 0x03D85 R W Rewrite byte count register Specify the number 1 of rewriting data can be set 0 to 63 P_WDATA_L P_WDATA_M 0x03D86 0x03D87 R W Rewrite data pointer register Specify the start address of RAM ...

Page 537: ...Byte Data in Data Area Specified one byte is programmed Protect_Set_Lib 0x6F210 Protective Function Setting Activate Protective Function in the specified address area Security_Key_Set_Lib 0x6F215 Key Code Setting Set key code 128 bits and activate Security Function Security_Key_Check_Lib 0x6F21A Key Code Authentication Authenticate the key code 128 bits and deactivate Security Function temporarily...

Page 538: ...Chapter 18 ReRAM XVIII 8 Command Library ...

Page 539: ...XIX Chapter 19 On Board Debugger 19 ...

Page 540: ...s used with the external debug unit PanaX EX It is unnecessary to implement the monitor program in user program area Refer to the following URL for the details of the on board debugging http www semicon panasonic co jp e micom onboard panax_ex html When LSI is connected to PanaX EX VDD18 is always set to 1 8V even when the 1 1V or 1 3V is set by software ...

Page 541: ...ring access so the real time performance slows down little Supported Back trace function Execute the back trace of stack frames and display the progress of function call Supported Event Factor Effective address Define address and range Supported 1 channel Data access Define access type R W data size 1 2 bytes data data mask range and NOT Break Forced Forced break Stop execution forcibly by pressin...

Page 542: ...Chapter 19 On Board Debugger XIX 4 List of on board debugging functions ...

Page 543: ...XX Chapter 20 Appendix 20 ...

Page 544: ...s Word 8 bits PC Program Counter 21 bits SP Stack Pointer 16 bits HA Handy Address 16 bits HA l Lower 8 bits of Handy Address HA h Higher 8 bits of Handy Address abs Absolute address used for general meaning abs8 Absolute address 8 bits abs12 Absolute address 12 bits abs16 Absolute address 16 bits abs18 Absolute address 18 bits abs20 Absolute address 20 bits Memory space specified by the contents ...

Page 545: ...t position LSB msb Bit position MSB io8 Displacement within the special function register area 0 to 255 IOTOP x 03F00 Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Bit inversion n n bit shift left n n bit shift right VF Overflow flag NF Negative flag CF Carry flag ZF Zero flag temp Temporary register Move Remainder Reflection of the operation result label...

Page 546: ...ion cycle becomes 2 2 0 2 cycles If the data access cycle is 3 d 2 then the execution cycle becomes 2 2 2 6 cycles EX 2 JSR label Cycle max 2 i 4 2d If the instruction fetch cycle is 2 i 1 and the data access cycle is 1 d 0 then the execution cycle becomes 2 1 4 2 0 4 cycles mem16 xxx 16 bit data in the memory specified by xxx sign xxx Sign extended data of xxx zero xxx Zero extended data of xxx d...

Page 547: ...em8 abs8 Dm mem8 abs12 Dm mem8 abs16 Dm Dn mem8 Am Dn mem8 d8 Am Dn mem8 d16 Am Dn mem8 d4 SP Dn mem8 d8 SP Dn mem8 d16 SP Dn mem8 IOTOP io8 Dn mem8 abs8 Dn mem8 abs12 Dn mem8 abs16 imm8 mem8 IOTOP io8 imm8 mem8 abs8 imm8 mem8 abs12 imm8 mem8 abs16 Dn mem8 HA mem16 An DWm mem16 An Am mem16 d4 SP DWm mem16 d4 SP Am mem16 d8 SP DWm mem16 d8 SP Am mem16 d16 SP DWm mem16 d16 SP Am mem16 abs8 DWm mem16...

Page 548: ...Dn CF Dm DWm DWn DWm Am DWn Am DWm imm16 DWm Am imm16 Am Dm Dn DWk DWm Dn DWm l DWm h Dm Dn PSW Dm imm8 PSW mem8 abs8 imm8 PSW mem8 abs12 imm8 PSW mem8 abs16 imm8 PSW DWm DWn PSW Am DWn PSW Am An PSW DWm imm16 PSW Am imm16 PSW Dm Dn Dm Dm imm8 Dm PSW imm8 PSW Dm Dn Dm Dm imm8 Dm PSW imm8 PSW Dm Dn Dm Dm imm8 Dm MOVW imm16 Am MOVW SP Am MOVW An SP MOVW DWn DWm MOVW DWn Am MOVW An DWm MOVW An Am PUS...

Page 549: ... 1 PC 4 d7 label H PC if ZF 0 PC 4 PC if ZF 1 PC 5 d11 label H PC if ZF 0 PC 5 PC if ZF 0 PC 3 d4 label H PC if ZF 1 PC 3 PC if ZF 0 PC 4 d7 label H PC if ZF 1 PC 4 PC if ZF 0 PC 5 d11 label H PC if ZF 1 PC 5 PC if VF NF 0 PC 4 d7 label H PC if VF NF 1 PC 4 PC if VF NF 0 PC 5 d11 label H PC if VF NF 1 PC 5 PC if CF 0 PC 4 d7 label H PC if CF 1 PC 4 PC if CF 0 PC 5 d11 label H PC if CF 1 PC 5 PC if...

Page 550: ... 1 PC 6 d11 label H PC if VF 0 PC 6 PC PC 3 d4 label H PC PC 4 d7 label H PC PC 5 d11 label H PC if Dm imm8 PC 6 d7 label H PC if Dm imm8 PC 6 PC if Dm imm8 PC 8 d11 label H PC if Dm imm8 PC 8 PC if mem8 abs8 imm8 PC 9 d7 label H PC if mem8 abs8 imm8 PC 9 PC if mem8 abs8 imm8 PC 10 d11 label H PC if mem8 abs8 imm8 PC 10 PC if mem8 abs16 imm8 PC 11 d7 label H PC if mem8 abs16 imm8 PC 11 PC if mem8 ...

Page 551: ...if mem8 abs16 bp 1 PC 10 d11 label H PC if mem8 abs16 bp 0 PC 10 PC 0 PC 19 16 An PC 15 0 0 PC H abs18 label H PC abs20 label H PC SP 3 SP PC 3 bp7 0 mem8 SP PC 3 bp15 8 mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 3 bp19 16 mem8 SP 2 bp3 0 0 PC bp19 16 An PC bp15 0 0 PC H SP 3 SP PC 5 bp7 0 mem8 SP PC 5 bp15 8 mem8 SP 1 PC 5 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 4 PC 5 bp19 16 mem8 SP 2 bp3 0 PC...

Page 552: ...mem8 SP 2 bp3 0 PC bp19 16 SP 3 SP mem8 SP PSW mem8 SP 1 PC bp7 0 mem8 SP 2 PC bp15 8 mem8 SP 3 bp7 PC H mem8 SP 3 bp3 0 PC bp19 16 mem8 SP 4 HA l mem8 SP 5 HA h SP 6 SP PC 2 PC imm3 1 RPC PSW x 3F PSW PSW x C0 PSW JSRV tbl4 RTS RTI NOP REP imm3 BE BD z z z z JSR RTS RTI NOP REP BE BD Group REP Notes Operation VF NF CF ZF Code Size Execution Cycle Machine Code MN101L SERIES INSTRUCTION SET Flag 1 ...

Page 553: ...MPW An Am MOV PSW Dm SUBW DWn DWm ADDW DWn DWm SUBW DWn Am CBEQ 8 Dm d11 CBNE 8 Dm d11 MOVW An Am MOVW An Am MOVW An DWm ADDW DWn Am MOVW DWn Am CMPW DWn Am MOV d16 SP Dm MOV Dn d16 SP MOV abs16 Dm MOV Dn abs16 MOVW DWn DWm NOPL n m MOV d8 SP Dm MOV Dn d8 SP CMPW DWn DWm MOV Dn PSW ADDUW Dn Am ADDSW Dn Am MOV d16 An Dm MOV Dn d16 Am NOT Dn ASR Dn ROR Dn LSR Dn REP 3 BTST 8 Dm MOVW SP Am EXT Dn DWm...

Page 554: ...Dm XOR Dn Dm XOR 8 Dm ADDC Dn Dm TBZ abs8 bp d11 TBNZ abs8 bp d7 TBNZ abs8 bp d11 TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 BSET io8 bp BSET abs16 bp BTST abs16 bp TBZ abs16 bp d11 TBNZ abs16 bp d11 TBZ abs16 bp d7 TBNZ abs16 bp d7 BCLR abs16 bp JMP abs18 label JSR abs18 label BCLR io8 bp TBNZ io8 bp d11 CMP 8 abs16 MOV 8 abs16 JMP abs20 label JSR abs20 label CBEQ 8 abs16 d7 d11 CBNE 8 abs16 d7 ...

Page 555: ...Chapter 20 Appendix Instruction map XX 13 ...

Page 556: ...Writing error correction NORMAL mode SCLK oscillation HALT0 mode SCLK oscillation NORMAL mode SCLK oscillation stop HALT0 mode SCLK oscillation stop Description addition 2 3 Note Description addition Do not perform the transition that is not listed in Figure 4 2 1 IV 16 Figure 4 2 5 Description addition Internal high speed oscillation stabili zation wait time Internal high speed oscillation stabil...

Page 557: ...25 C DC Char acteristics C10 Specification addition Supply current in HALT IDD10 MIN TYP 0 2 µA MAX 0 4 µA C11 to C14 Description change C10 IDD10 to C13 IDD13 C11 IDD11 to C14 IDD14 IV 12 Figure 4 1 2 Writing error correction Set the Clock mode Control Register CLKMD bit6 4 100 Set the Clock mode Control Register CLKMD bit6 4 010 IV 30 Setting Example of Writing error correction CPU outage in vol...

Page 558: ...mA Operating supply current IDD6 MAX 0 36 mA I 25 C9 Specification change Supply current in HALT IDD9 MAX 0 48 mA Supply current in HALT IDD9 MAX 0 33 mA C12 Specification change Supply current in STOP IDD12 MAX 0 12 µA Supply current in STOP IDD12 MAX 0 24 µA I 37 Recom mended Con dition of Each Pin DMOD Description change the value of which is typically between 100 Ω and 1000 Ω the value of whic...

Page 559: ...Diagram from CPU Operating Mode to HALT0 HALT1 Mode Figure 4 2 10 Transition from CPU Operating Mode to HALT0 HALT1 HALT2 Mode IV 20 Figure 4 2 11 Description change HALTMOD 1 HALT 1 Set the CPUM as described in Table 4 1 3 Description deletion Note 1 If it can t be guaranteed that Note 2 Insert 3 NOP instructions right after Note Description change If priority level of the interrupt to be used is...

Page 560: ... fSCLK 000 8 fSCLK 244 µs at fSCLK 111 512 fSCLK 15625 µs at fSCLK IV 27 Note 2 Description addition Only the clock supplied to CPU is halted VII 40 VII 43 VII 46 VII 49 VII 52 VII 55 Table 7 6 1 Table 7 7 1 Table 7 8 1 Table 7 9 1 Table 7 10 1 Table 7 11 1 remark Writing error correction The assignment and selection of 17 2 3 LCD Port Control Registers The assignment and selection of 17 2 2 LCD P...

Page 561: ...semicon panasonic co jp e micom Colophon Inquiries If you have questions regarding technical information on this manual please visit the following URL Panasonic Corporation URL http www semicon panasonic co jp en MN101LR05D 04D 03D 02D LSI User s Manual October 7 2013 1st Edition 5th Printing ...

Page 562: ...010413 Printed in Japan 1 Kotari yakemachi Nagaokakyo City Kyoto 617 8520 Japan Tel 81 75 951 8151 http www semicon panasonic co jp en ...

Page 563: ... 401 Building No 5 JiuGe Business Center Lane 2301 Yishan Rd Minhang District Shanghai China Sales Direct 86 21 6401 6692 Email amall ameya360 com QQ 800077892 Skype ameyasales1 ameyasales2 Customer Service Email service ameya360 com Partnership Tel 86 21 64016692 8333 Email mkt ameya360 com ...

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