No. SX-DSV02829 -
154-
Error No.
Protective
function
Causes
Measures
Main
Sub
81
0
Synchronization
cycle error
protection
If set to cycle synchronization(SYNC0 cycle or an IRQ
cycle) is not supported.
- It sets except 250000, 500000, 1000000,
2000000, and 4000000 [ns] to ESC
register SYNC0 Cycle Time (09A0h) and object
1C32h:sub 02h (Cycle time).
- The setting of an ESC register and an object is not in
agreement.
- Please set up a synchronous period correctly.
1
Mailbox error
protection
SM setting of Mailbox is wrong.
A setup of SM0/1 was set as the unjust value.
- A Physical Start Address:ESC register (0800h,
0801h/0808h, 0809h) setup of SyncManager0/1 is
inaccurate.
- The area for reception of Mailbox overlaps the area for
transmission.
- The area for transmission/reception of Mailbox overlaps
the area for transmission/reception of SyncManager2/3
- Address specification of the area for
transmission/reception of Mailbox is odd number.
- The start address of Mailbox is out of range from
SyncManager0: 1000h to 10FFh and SyncManager1:
1200h to 12FFh.
- A Length:ESC register (0802h,0803h/080Ah, 080Bh)
setup of SyncManager0/1 is inaccurate.
- Out of range from SyncManager0: 32 to 256 byte
- Out of range from SyncManager1: 40 to 256 byte
- A Control Register:ESC register (0804h/080Ch) setup of
SyncManager0/1 is inaccurate.
- Other than 100110b is set for 0804h: bit5-0.
- Other than 100010b is set for 080Ch: bit5-0.
- Please set up Sync manager correctly.
4
PDO watchdog
error protection
A setup of the watchdog timer of PDO is wrong.
- Although PDO watch dog trigger is effective
(SyncManager: Bit6 which is the register 0804h set to 1),
When the detection timeout value of PDO watchdog
timer cycle setup (registers 0400h and 0420h) was the
"communication cycle multiply 2" by DC and SM2 mode,
was the following was set as less than 2 ms by FreeRun
mode.
- Set up detection timeout value of watchdog timer correctly.
5
DC error
protection
DC setting setup is wrong.
- A value other than the following was set to bit 2-0 of
0981h (Activation) of the ESC register:
Bit 2-0 = 000b
Bit 2-0 = 011b
- Check setting of DC mode.
6
SM event mode
error protection
SM event mode which is not supported was set up.
- It was set to 1C32h-01h(Sync mode) at values other than
00h(FreeRun), 01h(SM2), and 02h(DC SYNC0).
- A value other than 00h (FreeRun), 02h (DC SYNC0), or 22h
(SM2) was set to 1C33h-01h (Sync mode).
- 000b was set to bit 2-0 of 0981h of the ESC register and SM2
was set to only either 1C32h-01h or 1C33h-01h.
- 1C32h-01h(Sync mode) should set up 00h(FreeRun),01h(SM2),
or 02h(DC SYNC0).
- 1C33h-01h(Sync mode) should set up 00h (FreeRun), 02h (DC
SYNC0), or 22h (SM2).
- The setting of 1C32h-01h should be equal to that of 1C33h-01h.
(To be continued)
R1.00
Motor Business Unit, Panasonic Corporation
