Panasonic KX-TDE200GR, Service Manual

Page: 73 / 132

73
KX-TDE200GR
KX-TDE
2
00
GR
IPCMPR CARD BLOCK DIAGRAM (2/2)
(1)
(3)
(5)
(7)
(8)
(10)
(12)
(14)
(16)
(18)
(20)
(22)
(23)
(25)
(27)
(28)
(30)
(32)
(33)
(35)
(37)
(39)
(41)
(42)
(43)
(45)
(46)
(48)
(49)
(51)
(53)
(55)
(56)
(58)
(60)
(62)
(63)
(65)
(66)
(67)
(2)
(4)
(6)
(11)
(13)
(15)
(17)
(19)
(21)
(24)
(26)
(29)
(31)
(34)
(36)
(38)
(40)
(44)
(47)
(50)
(52)
(54)
(57)
(59)
(61)
(64)
(9)
EC_AD[0-15]
EC_PAR
EC_nCBE1
EC_nCBE0
EC_nFRAME
EC_nPERR
EC_nSTOP
EC_nTRDY
EC_nINT
EC_CLK
EC_nCDET
RINGER
CT_NETAEF
CT_D[0-7]
DG
+3.3VD
+15V
MASTER/nS
M/nS
POWER_TYPE1
POWER_TYPE0
+3.3VD
DG
+2.5VD
+3.3VD
+3.3VD_B
+3.3VD_B
RS232_RTS2_CON
RS232_CTS2_CON
RS232_TXD2_CON
RS232_RXD2_CON
RS232_DTR2_CON
RS232_DSR2_CON
+15V
SHELF_FAN_ALM_FPGA
DC_ALM_FPGA
LED_RUN_FPGA_DRIVE
AC_ALM_FPGA
nHALT_FPGA
nFAN_ALM_FPGA
nLOS_FPGA
nBATT_FPGA
RINGER_SYNC_FPGA
LED_ALM_FPGA_DRIVE
CT_D[0]
CT_C8
CT_FRAME
nBUSY
EX1_D[15]
CLK_SD_33.33MHz SD0_nRESET_SOFT
RS232_DCD2_CON
CLK_32.768kHz
RMT_nRESET_SOFT
+15V_CON
+3.3VD_BB
+3.3VD
DG
DG
+3.3VD
EX1_A[1-7]
HWCLK[1]
CLKIO_66.66MHZ
+1.8VD
+1.25VD
+1.2VD
NEXUS_nRESET_SOFT
SHW_FH SHW_CLK LUHW[1] LDHW[1]
CH_SEL[3]
CH_SEL[0]
CH_SEL[1]
MELODYSEL
MOHSEL
CH_SEL[5]
+3.3VD
DG
+15V
VREF_7.5V
Mu/nA
CH_SEL[7] CH_SEL[6]
LUHW[0]
LDHW[0]
HW_CLK[0]
SVM_DSP_OUT[1]
SVM_DSP_OUT[0]
VOX[0-3]
CH_SEL[4]
HWFH
MEMORY_CARD_PRESNT
RTC_nINT
nBAT_ALM
CL3162
CL3164
CL3144
CL3172
CL3160
CL3180
CL3169
CL3159
DG
CL3173
CL3166
DG
DG
CL3146
TP_DRAM_VREF
CL3182
CL3178
CL3157
CL3171
CL3158
CL3176
CL3167
CL3179
DG
CL3177
CL3175
TP_+1.2VD
CL3168
CL3143
CL3174
CL3170
CL3165
CL3163
CL3181
CL3161
CL3149 CL3148 CL3152 CL3151
CL3145 CL3147
MAIN No.7
+3.3VD
CLK_SD_33.33MHz
DG
EX1_A[1-7]
EX1_D[0-15]
nDR
RS232_nDCD2
RS232_nDSR2
RS232_nDTR2
RS232_RXD2
RS232_TXD2
RS232_nCTS2
RS232_nRTS2
SD0_nINT
SD0_WP
SD0_CD
nCS_SD0
SD0_nRESET_SOFT
nWE0
SD0_DACK
SD0_nDRQ
RS232_RTS2_CON
RS232_TXD2_CON
RS232_RXD2_CON
RS232_CTS2_CON
RS232_DTR2_CON
RS232_DCD2_CON
RS232_DSR2_CON
MCCLK
MCDAT
MCCMD
TP_+1.25VD
TP_+2.5VD
TP_+3.3VD
TP_+3.3VD_B
TP_+15V
DG
CL3150 CL3153
CL3195
CL3194
CL3199
CL3192
CL3196
CL3198
CL3193
CL3191
CL3197
CL3190
CL3185
CL3189
CL3188
CL3186
CL3183
CL3184
CL3187
CL3155 CL3154
TP_+15V_CON
TP_+3.3VD_BB
TP_+1.8VD
MAIN No.10
+3.3VD
DG
EC_AD[0-15]
EC_PAR
EC_nCBE0
EC_nCBE1
EC_nRST
EC_nSTOP
EC_nTRDY
EC_nFRAME
EC_nPERR
EC_nINT
EC_nCDET
EC_CLK
+15V_CON
CT_FRAME
CT_NETAEF
CT_C8
RINGER
DC_ALM_FPGA
AC_ALM_FPGA
RS232_RTS2_CON
RS232_TXD2_CON
RS232_RXD2_CON
RS232_CTS2_CON
RS232_DTR2_CON
RS232_DCD2_CON
RS232_DSR2_CON
+3.3VD_BB
SHW_CLK
SHW_FH
CT_D[0-7]
M/nS_FPGA
LDHW[1]
LUHW[1]
nFAN_ALM_FPGA
LED_ALM_FPGA
LED_RUN_FPGA
MASTER/nS_FPGA
nBATT_FPGA
POWER_TYPE1_FPGA
POWER_TYPE0_FPGA
RINGER_SYNC_FPGA
nHALT_FPGA
nLOS_FPGA
SHELF_nFAN_ALM_FPGA
CL3202 CL3201 CL3200
MAIN No.9
+15V
+3.3VD
CH_SEL[0]
DG
HWCLK[0]
LDHW[0]
LUHW[0]
MELODYSEL
MOHSEL
Mu/nA
CH_SEL[1]
VREF_7.5V
DG
CL3204
CL3203
MAIN No.8
+3.3VD
CLK_NEXUS_66MHz
DG
EX2_A[0-21]
EX2_D[0-15]
EX2_nDR
HWCLK[0]
LDHW[0] LUHW[0]
nBS
NEXUS_nINT
SRAM_nBC1
SRAM_nBC0
SRAM_nWR
nBACK
nBREQ
SRAM_nCS
nCS_NEXUS
nBUSY
nRESET_SOFT
nWE1
nWE0
CH_SEL[0]
MELODYSEL
MOHSEL
Mu/nA
+3.3VD_B
EC_AD[0-15]
EC_PAR
EC_nCBE0
EC_nCBE1
EC_nSTOP
EC_nTRDY
EC_nFRAME
EC_nPERR
EC_nINT
EC_nCDET
EC_CLK
CT_D[0-7]
CT_FRAME
CT_NETAEF
CT_C8
RINGER
nRESET_POWER
LDHW[1]
HWFH
LUHW[1]
CH_SEL[4] SHW_CLK
SHW_FH
POWER_TYPE0
POWER_TYPE1
M/nS
MASTER/nS
HWCLK[1]
CH_SEL[1]
RMT_nRESET_SOFT
CH_SEL[3] CH_SEL[5] CH_SEL[6] CH_SEL[7]
VOX[0-3]
nCS_SRAM
MEMORY_CARD_PRESNT
EXT_nINT0
CL3207
MAIN No.13
+3.3VD
+3.3VD_B
DG
nRESET_POWER
+15V
+3.3VD_BB
+15V_CON
HARD_nRESET_SW +1.25VD
+1.2VD
+2.5VD
DRAM_VREF
+1.8VD
nBAT_ALM
MAIN No.4
CLKIO_66.66MHz CLK_SD_33.33MHz EX1_D[0-7] FAN_ALARM_nINT AC_ALARM_nINT DC_ALARM_nINT nRD nWE1 nWE0 nRDY_CPU nBUSY_NEXUS nCS_FPGA CLK_32.768kHz
nLOS_FPGA
nHALT_FPGA
RINGER_SYNC_FPGA
DC_ALM_FPGA
AC_ALM_FPGA
nBATT_FPGA
LED_RUN_FPGA_DRIVE
LED_ALM_FPGA_DRIVE
nFAN_ALM_FPGA
NEXUS_nRESET_SOFT PLD_TDI PLD_TCK SD0_nRESET_SOFT PLD_TMS PLD_TDO FPGA_INT RMT_nRESET_SOFT
SHELF_nFAN_ALM_FPGA
EX1_A[0-25] EX1_A-1
HWFH_NEXUS
LUHW0_NEXUS
LDHW0_NEXUS
HW_CLK0_NEXUS
CPU_nRESET
CT_D[0]
CT_FRAME
CT_C8
nCS_SRAM nCS_FLASH PROG_B
CH_SEL[5]
CH_SEL[6]
CH_SEL[7]
SVM_DSP_OUT[0]
SVM_DSP_OUT[1]
RTC_nINT nBACK nBAT_ALM
MAIN No.15
+15V
+3.3VD
DG
HWCLK[0]
LDHW[0]
Mu/nA
CH_SEL[6]
CH_SEL[7]
SVM_DSP_OUT[0]
SVM_DSP_OUT[1]
VOX[0-3]
VREF_7.5V
+3.3VD
+3.3VD
+15V
+3.3VD
+3.3VD
+1.25VD
+3.3VD_B
+3.3VD
+1.2VD
+3.3VD
+3.3VD_B
+15V
+2.5VD
+15V
+1.8VD
SD&RS232
NEXUS(+SRAM)
POWER
CODEC
EC_CT CON
FPGA+RTC+SVM
SVM_VOX
3.3V
0