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LTDVE4CH-20 | INSTRUCTIONS MANUAL
13. Wiring diagrams ................................................................................... 21
13.1. Wiring example #1: controller triggers camera .................................................................. 21
13.2. Wiring example #2: camera triggers controller .................................................................. 22
14. Operation .............................................................................................. 23
14.1. Operation with Modbus .................................................................................................... 23
14.1.1. Comparison of Modbus/RTU, Modbus/TCP and Modbus/UDP .................................. 23
14.1.2. Supported function codes .......................................................................................... 23
14.1.3. Read Holding Registers (0x03) .................................................................................. 24
14.1.4. Write Single Register (0x06) ...................................................................................... 24
14.1.5. Write Multiple Registers (0x10) .................................................................................. 24
14.2. Register file ...................................................................................................................... 24
14.2.1. Register DEVICE_TYPE............................................................................................ 34
14.2.2. Register BOOT_VERSION ........................................................................................ 35
14.2.3. Register MCU_VERSION .......................................................................................... 35
14.2.4. Register FPGA_VERSION ........................................................................................ 35
14.2.5. Register BOARD_VERSION ..................................................................................... 35
14.2.6. Register OSC_PERIOD ............................................................................................. 35
14.2.7. Registers FILTER_SEL[0:3] ....................................................................................... 35
14.2.8. Registers INPUT_SEL[0:7] ........................................................................................ 35
14.2.9. Registers GEN_DLY_BASE[0:7] ................................................................................ 36
14.2.10. Registers GEN_DLY_CNT[0:7] ................................................................................ 37
14.2.11. Registers GEN_WDT_BASE[0:7] ............................................................................ 37
14.2.12. Registers GEN_WDT_CNT[0:7] .............................................................................. 38
14.2.13. Registers OUTPUT_SEL_HI[0:3] and OUTPUT_SEL_HI[8:11] ................................ 38
14.2.14. Registers OUTPUT_SEL_LO[0:3] and OUTPUT_SEL_LO[8:11] ............................. 39
14.2.15. Registers PRT_CNT_ON[0:3] .................................................................................. 39
14.2.16. Registers PRT_ENA_ON[0:3] .................................................................................. 40
14.2.17. Registers PRT_CNT_OFF[0:3] ................................................................................ 40
14.2.18. Registers PRT_ENA_OFF[0:3] ................................................................................ 40
14.2.19. Registers CUR_RANGE[0:3] ................................................................................... 40
14.2.20. Registers CUR_VALUE[0:3] .................................................................................... 41
14.2.21. Register RS485_MODBUS_ADDR .......................................................................... 41
14.2.22. Register RS485_LINE_SPEED ............................................................................... 41
14.2.23. Register RS485_LINE_PARITY ............................................................................... 42
14.2.24. Registers ETH_MAC_ADDR[0:2] ............................................................................ 42
14.2.25. Registers ETH_HOSTNAME[0:7] ............................................................................ 42
14.2.26. Register ETH_DHCP_ENABLE ............................................................................... 43
14.2.27. Register ETH_IP_ADDR_HI .................................................................................... 43
14.2.28. Register ETH_IP_ADDR_LO ................................................................................... 43
