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IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A11
A9
A8
A13
A14
A17
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
A4
CE
A10
CE
O7
O6
O5
O4
O3
GND
O2
O1
O0
A0
A1
A2
A3
MX27L2000
32 TSO (8 x 20mm)
CONTROL
LOGIC
OUTPUT
BUFFERS
Y-DECODER
X-DECODER
Y-SELECT
2M BIT
CELL
MATRIX
VCC
VSS
CE
PGM
CE
A0-A17
ADDRESS
INPUTS
O0-O7
BLOCK DIAGRAM
PIN LAYOUT
SYMBOL
A0-A17
O0-O7
CE
OE
PGM
VPP
NC
VCC
GND
PIN NAME
Address Input
Data input/ Output
Chip Enable Input
Output Enable Input
Programmable Enable Input
Program Supply Voltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
PIN DESCRIPTION
Q8611 : MX27L2000 (2M BIT (256Kx8) CMOS EPROM