DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-30
Q604 MX29LV320AT/B (32Mbit CMOS Flash memory)
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
MX29LV320AT/B
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER
Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0~A20
WE
OE
WP
RESET
BYTE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE
GND
CE
A0
BLOCK DIAGRAM
SYMBOL
PIN NAME
A0~A20
Address Input
Q0~Q14
Data Input/Output
CE
Chip Enable Input
WE
Write Enable Input
RESET
Hardware Reset Pin/Sector Protect Unlock
OE
Output Enable Input
VCC
Power Supply Pin (+5V)
GND
Ground Pin
Q15/A-1
BYTE
RY/BY
WP/ACC
Hardware Write Protect/Acceleration Pin
Q15:Data Input/Output,word mode
A-1:LSB Address Input,byte mode
Word/Byte Selection Pin
Read/Busy output
PIN DESCRIPTION
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TEL 13942296513
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TEL 13942296513 QQ 376315150 892498299