DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-24
IC2001: M65776AFP (DVDM ASSY:IC751)-2
No.
Pin Name
Dir.
Pin Functions
201-208
2
3
4
5
84-87
90-95
97102
53-55
58-63
65,67,69
66,68
70
73
74
75
76
77
78
82
83
80
79
183
182
157,158,
184-186
188-192
178
179
177
169
176
159
173
161
160
IN
IN
IN
OUT
IN
I/O
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
BD[7:0]
BCLK
BDEN
BDREQ
BSECH
MD[15:0]
MA[11:0]
MBA[1:0]
DCS
DCS2
DCS3
DCS4
DCS5
RAS
CAS
DQMU
DQML
DWE
MCLK
PXCLK
PXCLKP
PD[7:0]
CSYNC
OSDKEY
PWD
AAD
DOCLK
LRCLK
DACCLK
CDBCK
CDLRCK
Bit stream data entry pin
Strobe signal of BD pin (clock)
This order effective / invalidity of data done a sample of by BD pin.
It is done a sample with a start edge of BCLK.
Data demand signal
This order it whether data of BD pin are with top byte of a sector.
Data transfer line with SDRAM
Address line of SDRAM
SDRAM bank choice line
Chip select of SDRAM
RAS (Row Address Strobe) control line of SDRAM
CAS (Column Address Strobe) control line of SDRAM
DQM control line of SDRAM
DQM control line of SDRAM
WE control line of SDRAM
Movement clock of SDRAM
27MHz pixel clock
54MHz pixel clock
Digital pixel data.
Y/Cb/Cr is done multiple of by 8 bit bus, and it is output.
Composite SYNC signal input terminal
OSD key flag output
The phase comparator output for external synchronization movement
Horizontal synchronizing signal output pin
Vertical synchronizing signal output pin
Serial PCM data for DAC
It output Lf/Rf data.
Serial PCM data for DAC
It output C/Sw data.
Serial PCM data for DAC
It output Ls/Rs data.
Serial PCM data for DAC
It is for the down mixture output.
Anciallary data output
PCM bit clock
Clock for channel distinction of pulse code modulation audio system data(L/R)
Exaggerated sample movement clock of DAC
The pulse code modulation bit clock which is input by CDDSP
The L/R clock which is input by CDDSP
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