DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-39
Q6101: DAC-3
FSC
MODULATION
S_HSYNC
S_VSYNC
S_BLANK
CLKIN_A
_HSYNC
P_VSYNC
P_BLANK
CLKIN_B
HD PIXEL
INPUT
SD PIXEL
INPUT
DE-
INTER-
LEAVE
Y
CB
CR
TEST
PATTERN
SHARPNESS
AND
ADAPTIVE
FILTER
CONTROL
Y COLOR
CR COLOR
CB COLOR
4:2:2
TO
4:4:4
TIMING
GENERATOR
TIMING
GENERATOR
DE-
INTER-
LEAVE
Y
CB
CR
TEST
PATTERN
DNR
GAMMA
COLOR
CONTROL
SYNC
INSER-
TION
CLOCK
CONTROL
AND PLL
UV SSAF
V
U
PS 4
HDTV 2
RGB
MATRIX
LUMA
AND
CHROMA
FILTERS
CGMS
WSS
DAC
DAC
DAC
DAC
DAC
DAC
SD 8
2 OVER-
SAMPLING
Block Diagram
TERMS USED IN THIS DATA SHEET
SD
Standard Definition Video, conforming to
ITU-R.BT601/ITU-R.BT656.
HD
High Definition Video, i.e., Progressive Scan or HDTV.
PS
Progressive Scan Video, conforming to SMPTE293M
or ITU-R.BT1358.
HDTV
High Definition Television Video, conforming to
SMPTE274M or SMPTE296M.
YCrCb
SD or HD Component Digital Video
YPrPb
HD Component Analog Video
YUV
SD Component Analog Video
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