DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-37
Q6101: DAC-1
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
V
DD_IO
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
V
DD
DGND
Y8
Y9
C0
C1
C2
S_BLANK
R
SET1
V
REF
COMP1
DAC A
DAC B
DAC C
V
AA
AGND
DAC D
DAC E
DAC F
COMP2
R
SET2
EXT_LF
RESET
C3
C4
I
2
C
ALSB
SDA
SCLK
P_HSYNC
P_VSYNC
P_BLANK
C5
C6
C7
C8
C9
R
T
C_SCR_TR
CLKIN_A
GND_IO
CLKN_B
S9
S8
S7
S6
S5
DGND
V
DD
S4
S3
S2
S1
S0
S_HSYNC
S_VSYNC
ADV7300A/ADV7301A
PIN FUNCTION DESCRIPTIONS
Block Diagram
PIN FUNCTION
Input/Output
Function
P
Power Supply for digital inputs and outputs.
I
10-Bit Progressive Scan/HDTV Input Port for Y data. The LSBs are set up on
Pins Y0 and Y1. In default mode, the input on this port is output on DAC D.
I
10-Bit Progressive Scan/HDTV Input Port for CrCb color data in 4:2:2 input
mode. In 4:4:4 Input Mode, this input port is used for the Cb (Blue/U) data.
The LSBs are set up on Pins C0 and C1. In default mode, the input on this
port is output on DAC E.
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9
8
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9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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