DV-CP802
IC BLOCK DIAGRAM AND TERMINAL DESCRIPTIONS-38
Q6101: DAC-2
19
I
2
C
This input pin must be tied high (V
DD_IO
) for the ADV7300A/ADV7301A to
interface over the I
2
C port.
20
ALSB
I/O
TTL Address Input. This signal sets up the LSB of the MPU address. When
this pin is tied low, the I
2
C filter is activated, which reduces noise on the I
2
C
interface.
21
SDA
I/O
MPU Port Serial Data Input/Output
22
SCLK
I
MPU Port Serial Interface Clock Input
23
P_HSYNC
I
Video Horizontal Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
24
P_VSYNC
I
Video Vertical Sync Control Signal for HD Sync in Simultaneous SD/HD
Mode and HD Only Mode
25
P_BLANK
I
Video Blanking Control Signal for HD Sync in Simultaneous SD/HD Mode
and HD Only Mode
31
RTC_SCR_TR
I
Multifunctional Input: Realtime Control (RTC) Input, Timing Reset Input,
and Subcarrier Reset Input
32
CLKIN_A
I
Pixel Clock Input for HD Only or SD Only Modes
33
RESET
I
This input resets the on-chip timing generator and sets the ADV7300A/
ADV7301A into default register setting. Reset is an active low signal.
34
EXT_LF
I
External Loop Filter for the internal PLL
35, 47
R
SET2, 1
I
A 760 resistor must be connected from this pin to AGND and is used to
control the amplitudes of the DAC outputs.
36, 45
COMP2, 1
O
Compensation Pin for DACs. Connect 0.1 F Capacitor from COMP Pin to V
AA
37
DAC F
O
In SD Only Mode: Chroma/Red/V Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pb/Blue (HD) Analog Output
38
DAC E
O
In SD Only Mode: Luma/Blue/U Analog Output, in HD Only Mode and
Simultaneous HD/SD: Pr/Red (HD) Analog Output
39
DAC D
O
In SD Only Mode: CVBS/Green/Y Analog Output, in HD Only Mode and
Simultaneous HD/SD: Y/Green (HD) Analog Output
40
AGND
G
Analog Ground
41
V
AA
P
Analog Power Supply
42
DAC C
O
Chroma/Red/V SD Analog Output
43
DAC B
O
Luma/Blue/U SD Analog Output
O
CVBS/Green/Y SD Analog Output
I/O
Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V)
I/O
Video Blanking Control Signal for SD
I/O
Video Vertical Control Signal for SD. Option to output SD VSYNC or SD
HSYNC in SD Slave Mode 0 and/or any HD Mode.
I/O
Video Horizontal Control Signal for SD. Option to output SD HSYNC or
HD HSYNC in SD Slave Mode 0 and/or any HD Mode.
I
10-Bit Standard Definition Input Port or Progressive Scan/HDTV Input Port
for Cr (Red/V) color data in 4:4:4 Input Mode. The LSBs are set up on Pins
S0 and S1. In Default Mode, the input on this port is output on DAC F.
56
V
DD
P
Digital Power Supply
57
DGND
G
Digital Ground
63
CLKIN_B
I
Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
Mode or a 74.25MHz (74.1758MHz) reference clock in HDTV Mode. This
clock input pin is only used in Simultaneous SD/HD Mode.
64
GND_IO
Pin No.
Mnemonic
Input/Output
Function
I
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