DV-CP701
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q1251: IC41LV16100-50T 16-MBIT DYNAMIC RAM
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
50
49
48
47
46
45
44
43
42
41
40
NC
NC
WE
RAS
NC
NC
A0
A1
A2
A3
VCC
VCC
I/O0
1/O1
1/O2
1/O3
VCC
1/O4
1/O5
1/O6
1/O7
NC
GND
1/O15
1/O14
1/O13
1/O12
GND
1/O11
1/O10
1/O9
1/O8
NC
NC
LCAS
UCAS
CE
A9
A8
A7
A6
A5
A4
GND
A0-A9
I/O0-15
WE
OE
RAS
UCAS
LCAS
VCC
GND
NC
Address input
Data inputs/outputs
Write enable
Output enable
Row address strobe
Upper column address strobe
Lower column address strobe
Power
Ground
No connection
PIN DESCRIPTION
PIN CONFIGURATION
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
REFRESH
COUNTER
ADDRESS
BUFFERS
R
O
W DECODER
MEMORY ARRAY
1.048.576 x 16
SENSE AMPLIFIERS
DATA I/O BUS
COLUMN DECODES
D
A
T
A
I/O B
UFFERS
WE
CONTROL
LOGICS
OE
CONTROL
LOGICS
CAS
RAS
OE
WE
LCAS
UCAS
RAS
FUNCTIONAL BLOCK DIAGRAM
WE
I/O0-I/O15
TRUTH TABLE
Function
RAS
LCAS
UCAS
WE
OE
Address t
R
/t
C
I/O
Standby
H
H
H
X
X
X
High-Z
Read: Word
L
L
L
H
L
ROW/COL
Dout
Read: Lower Byte
L
L
H
H
L
ROW/COL
Lower Byte. Dout
Upper Byte, High-Z
Read: Upper Byte
L
H
L
H
L
ROW/COL
Lower Byte, High-Z
Upper Byte. Dout
Write: Word (Early Write)
L
L
L
L
X
ROW/COL
Din
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW/COL
Lower Byte. Din
Upper Byte, High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
Lower Byte, High-Z
Upper Byte. Din
Read Write
L
L
L
H L
H L
ROW/COL
Dout, Din
EDO Page-Mode Read
1st Cycle
L
H L
H L
H
L
ROW/COL
Dout
2nd Cycle
L
H L
H L
H
L
NA/COL
Dout
Any Cycle
L
L H
L H
H
L
NA/NA
Dout
EDO Page-Mode Read
1st Cycle
L
H L
H L
L
X
ROW/COL
Din
2nd Cycle
L
H L
H L
L
X
NA/COL
Din
EDO Page-Mode
1st Cycle
L
H L
H L
H L
L
ROW/COL
Dout, Din
Read-Write
2nd Cycle
L
H L
H L
H L
L H
NA/COL
Dout, Din
Hidden Refresh
1st Cycle
L H L
L
L
H
L
ROW/COL
Dout
2nd Cycle
L H L
L
L
L
X
ROW/COL
Dout
RAS-Only Refresh
L
H
H
X
X
ROW/NA
High-Z
CBR Refresh
H L
L
L
X
X
X
High-Z
