DV-CP701
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q2301: TC74VCX162373FT 16-BIT D-TYPE LATCH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
PIN ASSIGNMENT
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
1D1
47
37
38
40
41
43
44
46
1D2
1D3
1D4
1D5
1D6
1D7
1D8
48
1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2
3
5
6
8
9
11
12
1LE
1OE
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
D
LE Q
2D1
36
26
27
29
30
32
33
35
2D2
2D3
2D4
2D5
2D6
2D7
2D8
25
24
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
13
14
16
17
19
20
22
23
2LE
2OE
Truth Table
Inputs
Outputs
1OE
H
L
L
L
1LE
X
L
H
H
1D1-1D8
X
X
L
H
1Q1-1Q8
Z
Qn
L
H
Inputs
Outputs
2OE
H
L
L
L
2LE
X
L
H
H
2D1-2D8
X
X
L
H
2Q1-2Q8
Z
Qn
L
H
X: Don't care
Z: High impedance
Qn: Q output are latched at the time
when the LE input is taken to a low logic level.
SYSTEM DIAGRAM