DV-CP701
IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
1
2
3
4
5
Q2002: S-80127CNMC-JKM VOLTAGE DETECTOR (12.7V N-ch open drain, Active L: out)
Q702: S-80130CLMC-JKM VOLTAGE DETECTOR (13.0V CMOS, Active L: out)
PIN CONFIGURATION
Top view
PIN DESCRIPTION
No.
1
2
3
4
5
Symbol
DS
VSS
NC
OUT
VDD
Description
ON/OFF switch for delay time
GND
Non-connection
Voltage detection output pin
Voltage input pin
*1
*1. NC pin is electrically open.
Oscillator
counter
timer
VREF
DELAY CIRCUIT
VDD
VSS
DS
OUT
BLOCK DIAGRAM
