
Pinouts
CD4051B (PDIP, CDIP, SOIC, TSSOP)
TOP VIEW
CD4052B (PDIP, CDIP, TSSOP)
TOP VIEW
CD4053B (PDIP, CDIP, TSSOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
4
6
COM OUT/IN
7
5
INH
V
SS
V
EE
V
DD
1
0
3
A
B
C
2
CHANNELS IN/OUT
CHANNELS
IN/OUT
CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
0
2
COMMON “Y” OUT/IN
3
1
INH
V
SS
V
EE
V
DD
1
COMMON “X” OUT/IN
0
3
A
B
2
Y CHANNELS
IN/OUT
Y CHANNELS
IN/OUT
X CHANNELS
IN/OUT
X CHANNELS
IN/OUT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
by
bx
cy
OUT/IN CX OR CY
IN/OUT CX
INH
V
SS
V
EE
V
DD
OUT/IN ax OR ay
ay
ax
A
B
C
OUT/IN bx OR by
IN/OUT
IN/OUT
Functional Block Diagrams
CD4051B
11
10
9
6
A
†
B
†
C
†
INH
†
13
4
2
5
1
12
15
14
TG
TG
TG
TG
TG
TG
TG
TG
3
COMMON
OUT/IN
0
1
2
3
4
5
6
7
BINARY
TO
1 OF 8
DECODER
WITH
INHIBIT
LOGIC
LEVEL
CONVERSION
8
7
V
SS
V
EE
16 V
DD
CHANNEL IN/OUT
†
All inputs are protected by standard CMOS protection network.
CD4051B, CD4052B, CD4053B
23
Summary of Contents for DT9904S
Page 1: ...SERVICE MANUAL DT9904S...
Page 4: ...3 7 9 2...
Page 12: ...7 MPEG BOARD CHECK WAVEFORM 7 1 27MHz WAVEFORM DIAGRAM 7 2 IC5L0380R PIN 2 WAVEFORM DIAGRAM 10...
Page 29: ...FRONT SCHEMATIC DIAGRAM 27...
Page 31: ...POWER BOARD SCHEMATIC DIAGRAM 29...
Page 33: ...OK SCHEMATIC DIAGRAM 31...
Page 35: ...OUTPUT BOARD SCHEMATIC DIAGRAM 33...
Page 40: ...MIAN SCHEMATIC DIAGRAM 38...
Page 47: ...11 APPENDIX AM FM Tuner Specificadtion 45...
Page 48: ...46...
Page 49: ...47...
Page 50: ...48...
Page 51: ...49...
Page 52: ...50...
Page 53: ...51...
Page 54: ...52...
Page 55: ...53...
Page 56: ...54...
Page 57: ...55...
Page 58: ...56...
Page 59: ...57...
Page 60: ...58...
Page 61: ...59...
Page 62: ...60...
Page 63: ...61...
Page 64: ...62...
Page 65: ...63...
Page 66: ...64...
Page 67: ...65...
Page 68: ...66...
Page 69: ...67...