![background image](http://html1.mh-extra.com/html/onkyo/dt9904s/dt9904s_service-manual_1636884018.webp)
HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
.
DESCRIPTION
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•
Single 3.3
±
0.3V power supply
Note)
•
All device pins are compatible with LVTTL interface
•
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•
All inputs and outputs referenced to positive edge of
system clock
•
Data mask function by UDQM or LDQM
•
Internal four banks operation
•
Auto refresh and self refresh
•
4096 refresh cycles / 64ms
•
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•
Programmable CAS Latency ; 2, 3 Clocks
8.1 HY57V641620HG
16
Summary of Contents for DT9904S
Page 1: ...SERVICE MANUAL DT9904S...
Page 4: ...3 7 9 2...
Page 12: ...7 MPEG BOARD CHECK WAVEFORM 7 1 27MHz WAVEFORM DIAGRAM 7 2 IC5L0380R PIN 2 WAVEFORM DIAGRAM 10...
Page 29: ...FRONT SCHEMATIC DIAGRAM 27...
Page 31: ...POWER BOARD SCHEMATIC DIAGRAM 29...
Page 33: ...OK SCHEMATIC DIAGRAM 31...
Page 35: ...OUTPUT BOARD SCHEMATIC DIAGRAM 33...
Page 40: ...MIAN SCHEMATIC DIAGRAM 38...
Page 47: ...11 APPENDIX AM FM Tuner Specificadtion 45...
Page 48: ...46...
Page 49: ...47...
Page 50: ...48...
Page 51: ...49...
Page 52: ...50...
Page 53: ...51...
Page 54: ...52...
Page 55: ...53...
Page 56: ...54...
Page 57: ...55...
Page 58: ...56...
Page 59: ...57...
Page 60: ...58...
Page 61: ...59...
Page 62: ...60...
Page 63: ...61...
Page 64: ...62...
Page 65: ...63...
Page 66: ...64...
Page 67: ...65...
Page 68: ...66...
Page 69: ...67...