ON Semiconductor NCP1239FDR2 Reference Manual Download

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NCP1239

http://onsemi.com

Figure 3. NCP1239F Internal Circuit Architecture

−

Vcc < 4V

450mV

0.5V / 0.25V

REF5V

SS / timer

PFC_Vcc

Fault
detect

Skip
adjust

Vdd

/ 3

to Skip

20k

0.9V

Oscillator

GND

32k

Drv

Vcc

Vdd

Regul

UVLOs
Latch
Reset

Error flag

Over Power
Limit

Vdd

2.5V

Vdd

2.5V

100k

Fault

Vdd

Soft−Start
and timer
management

Stby_detect

Error_Flag

Stby

OVL

Vcc<7V

stdwn

Vstop

PWM Latch

Output
Buffer

BO_out

Jittering
Modulation

“Jittered”
Reference

Jittering
Modulation

CLK

0.5V

BO_in

Soft−Start
Ipk limit

Internal
Thermal
Shutdown

TSD

Divider by 2

−

Skip

Startup Phase

(Vcc<VccOFF)

1mA

Vcc

10k

Vstop

regOUT

Stby_detect

25r

15r

FB<Vpin1 => Skip high

FB>1.6*Vpin1 =>Stby_detect RESET

pfcOFF

pfcON

UVLO

14V

clamp

pfcON

OUTon

Ramp
Compensation

3.2V

BO_in

A/V x V

pin5

LEB

−

Summary of Contents for NCP1239FDR2

Page 1: ...eriod Internal Frequency Dithering for Improved EMI Signature Go to Standby Signal for PFC Front Stage Large VCC Operation from 12 2 V to 36 V 500 mV Overcurrent Limit 500 mA 800 mA Peak Current Capab...

Page 2: ...OVP GND Vout Rbo1 GND Rcomp Cbo 5 12 6 7 8 11 10 9 Rramp VCC REF5V REF5V 5V 10mA Css Rbo2 Rt NTC Thermistor Figure 2 NCP1239V Typical Application Example Cbulk Vbulk to PFC_VCC BO 1 16 2 3 4 15 14 13...

Page 3: ...CC Going up 13 15 5 16 4 17 5 V VCCOFF Minimum Operating Voltage after Turn on 13 10 5 11 2 12 2 V HYST1 Difference VCCON VCCOFF 13 4 5 5 1 V VCCLATCH VCC Decreasing Level at which the Latch off Phase...

Page 4: ...aded by 1 nF 10 130 220 ns TLEB 65kHz Leading Edge Blanking Duration Pins 9 and 10 65 kHz NCP1239F 9 10 420 ns TLEB 130kHz Leading Edge Blanking Duration Pins 9 and 10 130 kHz NCP1239F 9 10 230 ns TLE...

Page 5: ...in standby state Pin 8 grounded Vpin6 4 5 V VCC 12 5 V 1 4 0 8 0 18 k Igts Sink Current Source in Normal Mode Vpin8 2 V Pin 7 open VCC Vpin1 0 7 V 1 0 6 1 0 mA FB skip Default Feedback Level for Skip...

Page 6: ...the fault is confirmed and the circuit enters an auto recovery burst mode otherwise the pin goes back to a lower value and oscillates to perform frequency jittering 7 Skip Adjust Adjust skip level By...

Page 7: ...nt Stby_detect Error_Flag Stby OVL OVL Vcc 7V stdwn Vstop PWM Latch Output Buffer BO_out Jittering Modulation Jittered Reference Jittering Modulation CLK CLK 0 5V BO_in Soft Start Ipk limit Soft Start...

Page 8: ...ment Stby_detect Error_Flag Stby OVL OVL Vcc 7V stdwn Vstop PWM Latch Output Buffer BO_out Jittering Modulation Jittered Reference Jittering Modulation CLK CLK BO_in Soft Start Ipk limit Soft Start Ip...

Page 9: ...STICS Figure 7 High Voltage Current Source vs Temperature VCC 0 V TEMPERATURE C 125 100 75 50 25 25 I C2 mA 6 0 0 5 0 4 0 3 0 2 0 1 0 0 Figure 8 High Voltage Pin Leakage Current vs Temperature 125 TEM...

Page 10: ...igure 13 NCP1239F Circuit Consumption 1 nF on driver Pin 12 vs Temperature 130 kHz 4 5 5 0 100 kHz 65 kHz 0 TEMPERATURE C 125 100 75 50 25 25 I CC2 mA Figure 14 NCP1239V Circuit Consumption 1 nF on dr...

Page 11: ...max K osc kHz k 130 kHz 77 78 80 82 Figure 19 Driver Voltage Clamp vs Temperature Figure 20 Maximum Duty Cycle vs Temperature NCP1239F Figure 21 Oscillator Kosc Parameter vs Temperature Kosc fsw Rpin4...

Page 12: ...Temperature NCP1239F 0 0 506 0 504 0 502 0 500 0 498 0 496 0 494 0 492 TEMPERATURE C 125 100 75 50 25 25 BO_H V 0 510 TEMPERATURE C 125 100 75 50 25 25 FB stby out mV 780 0 0 TEMPERATURE C 125 100 75...

Page 13: ...Figure 30 Fault Detect Threshold vs Temperature TEMPERATURE C 125 100 75 50 25 Dmax 24 5 0 Figure 31 Maximum Duty Cycle vs Temperature Vpin9 1 V NCP1239V Figure 32 Kdmax Coefficient vs Temperature Vpi...

Page 14: ...100ms Fault confirmed New Startup attempt SS timer pin 0 9 V Error flag 0 9 V Error flag Fault Management This time is programmed by the Pin 6 capacitor Cpin6 390 nF nearly sets the following interva...

Page 15: ...ect latch is reset 100ms 100ms delay FB skip Vpin7 FB stby out 1 7 Vpin7 4 3V 3 0V 1 8V Bunches of pulses Standby Detection This time is programmed by the Pin 6 capacitor Cpin6 390 nF nearly sets the...

Page 16: ...tage The NCP1239 incorporates an internal logic that is able to detect a standby situation Pin1 state changes in accordance to the detected mode standby or normal mode Simply connect a pnp transistor...

Page 17: ...e 0 9 V setpoint clamp during the startup period but also anytime an overload occurs an internal error flag is asserted testifying that the system is pushed to the maximum power At that moment a 100 m...

Page 18: ...rt Time Tss 7 5 ms Jittering Period Tjittering 10 ms Fault Detection Delay Tdelay 100 ms More generally the times approximately depend on Cpin6 as follows Tss 7 5 ms Cpin6 390 nF Tjittering 10 ms Cpin...

Page 19: ...e maximum peak setpoint is reached the internal 0 9 V Zener diode actively clamping the current amplitude to 0 9 V Rsense During this time the NCP1239 asserts an error flag A maximum current condition...

Page 20: ...ely depend on Cpin6 as follows Tss 7 5 ms Cpin6 390 nF Tjittering 10 ms Cpin6 390 nF Tdelay 100 ms Cpin6 390 nF Figure 38 Vcc PWM Timer 0 9V flag PFC Vcc regulation 100ms 16 4V 11 2V 6 9V 100ms 100ms...

Page 21: ...dependently of the auxiliary voltage level In auxiliary supply based power supplies it is necessary that the isolated secondary output conditions properly reflects on the non isolated auxiliary windin...

Page 22: ...rted high a 100 ms timer gets started If the error flag keeps asserted during the 100 ms period then the controller detects a true fault condition and stops pulsing the output If this is a simple tran...

Page 23: ...s the pulses flow The 100 ms delay could be shortened or lengthened by changing the Pin 6 capacitor VCCOFF VCC VCCON Figure 42 Drv 100ms 100ms t1 t2 t3 t 1 t 2 Latch off phase level Logic reset level...

Page 24: ...CC higher than VCCOFF As a consequence the final duty cycle is lower than previously estimated longer than the switching phase period In this case the circuit detects an overload condition simply beca...

Page 25: ...to be detected If the thermistor is a PTC it must be placed between Pin 3 and ground One must place a resistor between the 5 V reference voltage and Pin 3 Similarly the resistor must be selected so th...

Page 26: ...ing VBO Vtrip 2 The best way to assess the right value of Cfil is to use a simple simulation sketch as the one depicted by Figure 46 A behavioral source loads the rectified DC line and adjusts itself...

Page 27: ...ine V timing Vline bulk V2 timing 0 PWL 0 0 2 3s 1 7s 1 10s 0 2 V1 line 0 SIN 0 150 50 PSpice EBbrown Value IF V CMP 3 250m 0 PSpice EBload Value IF V CMP 3 35 V bulk 0 A simple simulation configurati...

Page 28: ...d to provide the output with more power than normally necessary To the light of these statements it becomes interesting to accurately limit the amount of power drawn from the AC line in fault conditio...

Page 29: ...that Pin 9 monitors the following voltage Vpin9 Rsense Ip Ipin9 Rcomp Ipin9 Ipin9 being small compared to the inductor current the Pin 9 voltage simplifies as follows Vpin9 Rsense Ip Rcomp Ipin9 Ipin...

Page 30: ...time Practically the Pin 9 voltage is compared to the positive ramp of the internal oscillator and the power switch is allowed to be on only when the ramp is below Vpin9 Then the maximum on time is g...

Page 31: ...activated when VCC ramps up either from zero fresh power on sequence or 6 9 V the latch off threshold after an overload detection OVL for instance Figure 51 shows the soft start behavior The time scal...

Page 32: ...he ramp is disabled during standby i e when pfcON is low This inhibition avoids that the ramp compensation modifies the setpoint above which the NCP1239 enables PFC Frequency Jittering Frequency jitte...

Page 33: ...s Lp primary inductance 350 H fsw switching frequency 65 kHz Ip skip 600 mA or 140 mV Rsense The theoretical power transfer is therefore 1 2 Lp Ip2 fsw 4 W If this IC enters skip cycle mode with a bun...

Page 34: ...econd comparator COMP2 compares the feedback voltage FB or Vpin8 to 1 7 Vpin7 As long as the load keeps light FB does not exceed 1 7 Vpin7 i e 0 74 V typical if no voltage is forced to Pin 7 A timer c...

Page 35: ...uctance of 250 H To pass 120 W we assume that a peak current of 4 2 A was needed Due to these numbers we can easily now when the GTS signal will be asserted Lp primary inductance 250 H 85 fsw switchin...

Page 36: ...VCC as soon as the FB pin voltage has gone below a threshold about 2 7 V that is when the internal error flag stops being asserted Figure 61 Overload Conditions The feedback voltage goes high and asse...

Page 37: ...As a consequence the FB pin voltage goes below the Vskip threshold and the soft start timer counts about 100 ms if Cpin6 330 nF When the 100 ms time has elapsed the PFC VCC stops being fed Figure 63...

Page 38: ...t convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the bo...

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