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NCP1219PRINTGEVB

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14

Overvoltage Protection

Overvoltage protection (OVP) is implemented on this

evaluation board using one of two options; primary side
overvoltage protection or secondary side overvoltage
protection.

Primary side OVP is implemented as shown in Figure 25.

With the auxiliary winding in a flyback configuration, V

CC

is proportional to the output voltage. A zener diode and
series current limiting resistor are connected between the
Skip/latch pin of the controller and V

CC

. If the output

voltage starts to rise, V

CC

 rises and current starts to flow

through ZD1. The zener current causes the voltage on the
Skip/latch pin to exceed the latch threshold and the
controller enters latched fault mode.

Figure 25. Primary Overvoltage Protection Circuit

R15

ZD1

D6

Skip/
latch

FB

CS

DRV

GND

VCC

HV

C7

R11

A secondary side OVP latch function is implemented

using the circuit shown in Figure 26. The primary and
secondary sides are isolated using an optocoupler. The zener
diode ZD2 starts to conduct if the output voltage exceeds the
regulated voltage. The current conducted by ZD2 biases Q3
and causes current to flow from the cathode of the
optocoupler. The optocoupler transistor turns on and the
voltage on the Skip/latch pin increases, latching the
controller. The value of R10 is chosen in order to limit the
voltage applied to the Skip/latch pin during a fault condition.

Figure 26. Secondary Overvoltage Protection Circuit

U2

Q3

R20

R30

C18

ZD2

Skip/
latch

FB

CS

DRV

GND

VCC

HV

R10

VCC

VHOUT

Latch Protection

The latching fault protection offered by the NCP1219 can

also be used to implement other convenient board level
protection functions besides the overvoltage protection

options included on this evaluation board. For example, the
latch pin may be used to implement temperature shutdown
externally using an NTC element driving the base of a
bipolar transistor, Q1, as shown in Figure 27. The NTC
value is chosen so that the voltage divider made between it
and R

be

 turn on Q1 at the proper temperature. Once the

controller enters a latched fault, V

CC

 must decrease lower

than V

CC(reset)

 to reset the controller. This is typically

achieved by removing power from the mains.

Figure 27. Temperature Shutdown Latch Circuit

Skip/

latch

FB

CS

DRV

GND

VCC

HV

NTC

R

be

Q1

Any other generic latched fault can be implemented using

a circuit similar to Figure 28. A fault signal is applied to the
base of an npn bipolar transistor, Q2, whose cathode drives
the base of a pnp bipolar transistor, Q1, bringing the
Skip/latch pin high.

Figure 28. Generic Latched Shutdown Example

Latch Off

Signal

Skip/

latch

FB

CS

DRV

GND

VCC

HV

Q1

Q2

SOFT

START

Soft

start reduces stress during power up by slowly

increasing the peak current until the soft

start timer expires.

The NCP1219 implements soft

start by comparing the CS

pin voltage to the lesser of the internal divided by three FB
voltage or the internal soft

start ramp. The soft

start

management block of the NCP1219 controller enables the
soft

start voltage ramp to rise in 4.8 ms. Figure 29 shows the

current sense waveform taken differentially across the sense
resistor, as the current ramps up during the first 4.8 ms of the
startup time.

Summary of Contents for NCP1219PRINTGEVB

Page 1: ...W output with transient capability of 48 W as defined in Figure 1 Figure 1 Transient Output Current Specification time ms Output Current A 0 92 A 2 0 A 1 25 A 700 ms 300 ms The system has a low voltag...

Page 2: ...10 R15 10 Q3 open R20 open R30 open R1 4 75M R2 4 75M MMSD914T1G C18 open C14 470pF 250V R18 100 D12 MUR420RLG R33 8 06k Q6 2N7002L R34 1k R35 10K C1 0 22mF 275V 1 2 HS1 ZD2 open Q5 SPA07N65C3 SGND JP...

Page 3: ...CCM the secondary RMS current is minimized reducing the requirements on the transformer and output capacitor For the evaluation board design with a transition occurring at Iout 1 6 A the primary induc...

Page 4: ...ating factor of 0 8 to PIV the minimum breakdown voltage of D12 must be greater than 173 V An MUR420 200 V ultrafast rectifier is selected The power dissipated in the secondary diode Pd is approximate...

Page 5: ...ircuitry to prevent the converter from entering DSS mode during the standby conditions Figure 3 shows this configuration The voltage is supplied by the auxiliary winding through a series diode Figure...

Page 6: ...the startup circuit is charging CCC The increased bulk voltage is given by Equation 23 Vbulk PDSS ICC3 Istart Rbulk eq 23 where PDSS is found by rearranging Equation 22 and using the RqJA measured abo...

Page 7: ...en the primary and secondary side of the converter The collector of the optocoupler is connected to the FB pin of the NCP1219 closing the feedback loop as shown in Figure 8 Figure 8 Feedback Network V...

Page 8: ...he TL431 and an optocoupler The tool takes system level inputs from the user such as bulk input voltage output voltage output current and controller switching frequency A screenshot of the parameter c...

Page 9: ...tool based on the power stage response optocoupler pole location and the type 2 compensation design The user can check the frequency response at various input voltages and load conditions to verify s...

Page 10: ...he zero frequency fz is calculated using Equation 29 fz fC k eq 29 The zero frequency is set to 240 Hz The bandwidth of the optocoupler can be used to set the pole location of the compensation network...

Page 11: ...10 20 30 70 200 160 120 80 40 0 40 80 120 160 200 PHASE Mag dB PM 60 fC 1 3 kHz Skip Mode for Reduced Standby Power Dissipation The NCP1219 employs an adjustable skip level that reduces input power i...

Page 12: ...ause audible noise On the other hand when the board is operating in standby mode and the load is very low a higher skip threshold minimizes the number of switching cycles per skip cycle This reduces s...

Page 13: ...36 The resulting sense voltage is 1 13 V Under high line conditions the desired overpower output current is 2 5 A 60 W Calculate the sense voltage associated with the desired output power using the sa...

Page 14: ...HV R10 VCC VHOUT Latch Protection The latching fault protection offered by the NCP1219 can also be used to implement other convenient board level protection functions besides the overvoltage protectio...

Page 15: ...ted using 2 oz copper During the layout process care was taken to 1 Minimize trace length especially for high current loops 2 Use wide traces for high current connections 3 Use a single ground connect...

Page 16: ...NCP1219PRINTGEVB http onsemi com 16 Figure 30 Layer 1 Top Figure 31 Layer 2 Bottom...

Page 17: ...en copper and soldermask The layout files may be available Please contact your sales representative for availability Design Validation The top and bottom view of the board are shown in Figures 32 and...

Page 18: ...C0G2J472J Yes Yes C14 1 Capacitor Ceramic Through Hole 470 pF 250 V 10 Radial TDK FK18C0G2E471J Yes Yes C15 1 Capacitor Electrolytic 1000 uF 35 V 20 Radial United Chemicon EKZE350ELL102MK25S Yes Yes C...

Page 19: ...Resistor SMD 1 4 MW 0 01 SM 1206 Vishay CRCW12061404FN Yes Yes R6 1 Resistor SMD 10 W 0 01 SM 1206 Vishay CRCW120610R0FN Yes Yes R9 1 Resistor Through Hole 20 W 0 01 Axial Yageo MFR 25FBF 20R0 Yes Yes...

Page 20: ...www epcos com 3 ICE Components can be ordered at http www icecomponents com 4 Infineon components can be ordered at http www infineon com 5 Kemet components can be ordered at http www kemet com 6 TDK...

Page 21: ...cause the forward auxiliary winding voltage is less than that required to maintain VCC greater than VCC MIN A portion of the standby input power is due to the startup circuit As the input voltage incr...

Page 22: ...kes of noise that are due to the switch transitions Figure 37 Output Voltage Ripple at High line and Full Load If the output ripple is observed on a longer time scale a component of the NCP1219 freque...

Page 23: ...n Figure 39 The output response to the load step is measured as 150 mV and recovery occurs in less than 5 ms Response to the transient load condition confirms the results of the loop stability analysi...

Page 24: ...Figures 40 through 43 show several images of the board during a continuous load step as described in Figure 1 Images include top and bottom layers at low and high line All images were taken in open ai...

Page 25: ...p onsemi com 25 Figure 42 Thermal Image of the Top of the Board at High Line During a Continuous Load Step Condition Figure 43 Thermal Image of the Bottom of the Board at High Line During a Continuous...

Page 26: ...0 W 48 W converter is designed and built using the flyback topology The converter is implemented using the NCP1219 The average load efficiency is measured above 83 5 over the complete operating range...

Page 27: ...inutes and start the integration cycle 20 Measure VOUT standby using the corresponding multimeter Record the results in Table 5 Verify it is within the limits of Table 4 21 Measure and the integrated...

Page 28: ...ble 4 DESIRED RESULTS Input Voltage IOUT For 115 Vac 60 Hz input 70 mA 7 V VOUT standby 8 V 70 mA PIN 1 W IOUT specified in Table 3 VOUT 24 0 2 V 25 50 75 100 havg 83 5 For 230 Vac 50 Hz input 70 mA 7...

Page 29: ...ication by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as component...

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