NCP1219PRINTGEVB
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14
Overvoltage Protection
Overvoltage protection (OVP) is implemented on this
evaluation board using one of two options; primary side
overvoltage protection or secondary side overvoltage
protection.
Primary side OVP is implemented as shown in Figure 25.
With the auxiliary winding in a flyback configuration, V
CC
is proportional to the output voltage. A zener diode and
series current limiting resistor are connected between the
Skip/latch pin of the controller and V
CC
. If the output
voltage starts to rise, V
CC
rises and current starts to flow
through ZD1. The zener current causes the voltage on the
Skip/latch pin to exceed the latch threshold and the
controller enters latched fault mode.
Figure 25. Primary Overvoltage Protection Circuit
R15
ZD1
D6
Skip/
latch
FB
CS
DRV
GND
VCC
HV
C7
R11
A secondary side OVP latch function is implemented
using the circuit shown in Figure 26. The primary and
secondary sides are isolated using an optocoupler. The zener
diode ZD2 starts to conduct if the output voltage exceeds the
regulated voltage. The current conducted by ZD2 biases Q3
and causes current to flow from the cathode of the
optocoupler. The optocoupler transistor turns on and the
voltage on the Skip/latch pin increases, latching the
controller. The value of R10 is chosen in order to limit the
voltage applied to the Skip/latch pin during a fault condition.
Figure 26. Secondary Overvoltage Protection Circuit
U2
Q3
R20
R30
C18
ZD2
Skip/
latch
FB
CS
DRV
GND
VCC
HV
R10
VCC
VHOUT
Latch Protection
The latching fault protection offered by the NCP1219 can
also be used to implement other convenient board level
protection functions besides the overvoltage protection
options included on this evaluation board. For example, the
latch pin may be used to implement temperature shutdown
externally using an NTC element driving the base of a
bipolar transistor, Q1, as shown in Figure 27. The NTC
value is chosen so that the voltage divider made between it
and R
be
turn on Q1 at the proper temperature. Once the
controller enters a latched fault, V
CC
must decrease lower
than V
CC(reset)
to reset the controller. This is typically
achieved by removing power from the mains.
Figure 27. Temperature Shutdown Latch Circuit
Skip/
latch
FB
CS
DRV
GND
VCC
HV
NTC
R
be
Q1
Any other generic latched fault can be implemented using
a circuit similar to Figure 28. A fault signal is applied to the
base of an npn bipolar transistor, Q2, whose cathode drives
the base of a pnp bipolar transistor, Q1, bringing the
Skip/latch pin high.
Figure 28. Generic Latched Shutdown Example
Latch Off
Signal
Skip/
latch
FB
CS
DRV
GND
VCC
HV
Q1
Q2
SOFT
−
START
Soft
−
start reduces stress during power up by slowly
increasing the peak current until the soft
−
start timer expires.
The NCP1219 implements soft
−
start by comparing the CS
pin voltage to the lesser of the internal divided by three FB
voltage or the internal soft
−
start ramp. The soft
−
start
management block of the NCP1219 controller enables the
soft
−
start voltage ramp to rise in 4.8 ms. Figure 29 shows the
current sense waveform taken differentially across the sense
resistor, as the current ramps up during the first 4.8 ms of the
startup time.