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NCP1219PRINTGEVB

http://onsemi.com

10

-6 0

-5 0

-4 0

-3 0

-2 0

-1 0

0

1 0

2 0

3 0

4 0

1

1 0

1 0 0

1 0 0 0

1 0 0 0 0

1 0 0 0 0 0

Frequency (Hz)

Mag (dB)

-3 0 0

-2 6 0

-2 2 0

-1 8 0

-1 4 0

-1 0 0

-6 0

-2 0

2 0

6 0

1 0 0

Mag (dB)

17 dB

Figure 17. Frequency Response of the Power Stage

Phase (

°

)

PHASE (

°

)

The pole introduced by the optocoupler needs to be

considered. The pole location is dependant on the biasing
conditions of the optocoupler. The internal 16.7 k

W

 pullup

resistor and the output capacitance of the optocoupler set the
pole at 4.7 kHz, as shown in Figure 14. The location of this
pole limits the available bandwidth of the system.

The evaluation board design uses the k

factor approach to

pole and zero placement, and a phase margin of 65

°

 is

chosen. For the type 2 compensation network, the k

factor

is found using Equation 27,

k

+

tan

ǒ

PM

*

PS

*

90

2

)

45

Ǔ

(eq. 27)

where PM is the desired phase margin, and PS is the phase
brought by the power stage. For a crossover frequency, f

c

, of

1 kHz, the phase caused by the power stage is 

88

°

. The

resulting k value is 4.2. The pole frequency, f

p

, is calculated

using Equation 28.

f

p

+

f

C

@

k

(eq. 28)

The pole frequency for this design is equal to 4.2 kHz. The

zero frequency, f

z

, is calculated using Equation 29,

f

z

+

f

C

k

(eq. 29)

The zero frequency is set to 240 Hz.

The bandwidth of the optocoupler can be used to set the

pole location of the compensation network. In this case,
adding capacitance to satisfy the k

factor calculations limits

the bandwidth of the system and causes slowing of the
transient response and increased output ripple. The
capacitance needed to place the zero is calculated using
Equation 30.

C

zero

+

1

2

@

p

@

f

z

@

R

upper

(eq. 30)

For this design, a value of 33 nF is chosen for C

zero

.

The required gain boost (G

fc

) needed to compensate the

system and provide a crossover frequency of 1 kHz is
measured as 17 dB. The gain provided by the compensation
network is calculated using Equation 31.

G

+

10

G

f

C

20

(eq. 31)

The R

LED

 value needed to produce this gain is calculated

using Equation 32.

R

LED

+

R

pullup

@

CTR

G

(eq. 32)

From the measurements and the resulting gain, R

LED

 is

990 

W

.

The open loop response is measured by injecting an ac

signal across R19 using a network analyzer and an isolation
transformer as shown in Figure 18. The open loop response
is the ratio of B to A.

Figure 18. Open Loop Frequency Response

Measurement Setup

The resulting loop response after compensation is shown

in Figure 19, where the crossover frequency is 1.3 kHz, with
a phase margin of 60

°

, measured at low

line and nominal

load current.

Summary of Contents for NCP1219PRINTGEVB

Page 1: ...W output with transient capability of 48 W as defined in Figure 1 Figure 1 Transient Output Current Specification time ms Output Current A 0 92 A 2 0 A 1 25 A 700 ms 300 ms The system has a low voltag...

Page 2: ...10 R15 10 Q3 open R20 open R30 open R1 4 75M R2 4 75M MMSD914T1G C18 open C14 470pF 250V R18 100 D12 MUR420RLG R33 8 06k Q6 2N7002L R34 1k R35 10K C1 0 22mF 275V 1 2 HS1 ZD2 open Q5 SPA07N65C3 SGND JP...

Page 3: ...CCM the secondary RMS current is minimized reducing the requirements on the transformer and output capacitor For the evaluation board design with a transition occurring at Iout 1 6 A the primary induc...

Page 4: ...ating factor of 0 8 to PIV the minimum breakdown voltage of D12 must be greater than 173 V An MUR420 200 V ultrafast rectifier is selected The power dissipated in the secondary diode Pd is approximate...

Page 5: ...ircuitry to prevent the converter from entering DSS mode during the standby conditions Figure 3 shows this configuration The voltage is supplied by the auxiliary winding through a series diode Figure...

Page 6: ...the startup circuit is charging CCC The increased bulk voltage is given by Equation 23 Vbulk PDSS ICC3 Istart Rbulk eq 23 where PDSS is found by rearranging Equation 22 and using the RqJA measured abo...

Page 7: ...en the primary and secondary side of the converter The collector of the optocoupler is connected to the FB pin of the NCP1219 closing the feedback loop as shown in Figure 8 Figure 8 Feedback Network V...

Page 8: ...he TL431 and an optocoupler The tool takes system level inputs from the user such as bulk input voltage output voltage output current and controller switching frequency A screenshot of the parameter c...

Page 9: ...tool based on the power stage response optocoupler pole location and the type 2 compensation design The user can check the frequency response at various input voltages and load conditions to verify s...

Page 10: ...he zero frequency fz is calculated using Equation 29 fz fC k eq 29 The zero frequency is set to 240 Hz The bandwidth of the optocoupler can be used to set the pole location of the compensation network...

Page 11: ...10 20 30 70 200 160 120 80 40 0 40 80 120 160 200 PHASE Mag dB PM 60 fC 1 3 kHz Skip Mode for Reduced Standby Power Dissipation The NCP1219 employs an adjustable skip level that reduces input power i...

Page 12: ...ause audible noise On the other hand when the board is operating in standby mode and the load is very low a higher skip threshold minimizes the number of switching cycles per skip cycle This reduces s...

Page 13: ...36 The resulting sense voltage is 1 13 V Under high line conditions the desired overpower output current is 2 5 A 60 W Calculate the sense voltage associated with the desired output power using the sa...

Page 14: ...HV R10 VCC VHOUT Latch Protection The latching fault protection offered by the NCP1219 can also be used to implement other convenient board level protection functions besides the overvoltage protectio...

Page 15: ...ted using 2 oz copper During the layout process care was taken to 1 Minimize trace length especially for high current loops 2 Use wide traces for high current connections 3 Use a single ground connect...

Page 16: ...NCP1219PRINTGEVB http onsemi com 16 Figure 30 Layer 1 Top Figure 31 Layer 2 Bottom...

Page 17: ...en copper and soldermask The layout files may be available Please contact your sales representative for availability Design Validation The top and bottom view of the board are shown in Figures 32 and...

Page 18: ...C0G2J472J Yes Yes C14 1 Capacitor Ceramic Through Hole 470 pF 250 V 10 Radial TDK FK18C0G2E471J Yes Yes C15 1 Capacitor Electrolytic 1000 uF 35 V 20 Radial United Chemicon EKZE350ELL102MK25S Yes Yes C...

Page 19: ...Resistor SMD 1 4 MW 0 01 SM 1206 Vishay CRCW12061404FN Yes Yes R6 1 Resistor SMD 10 W 0 01 SM 1206 Vishay CRCW120610R0FN Yes Yes R9 1 Resistor Through Hole 20 W 0 01 Axial Yageo MFR 25FBF 20R0 Yes Yes...

Page 20: ...www epcos com 3 ICE Components can be ordered at http www icecomponents com 4 Infineon components can be ordered at http www infineon com 5 Kemet components can be ordered at http www kemet com 6 TDK...

Page 21: ...cause the forward auxiliary winding voltage is less than that required to maintain VCC greater than VCC MIN A portion of the standby input power is due to the startup circuit As the input voltage incr...

Page 22: ...kes of noise that are due to the switch transitions Figure 37 Output Voltage Ripple at High line and Full Load If the output ripple is observed on a longer time scale a component of the NCP1219 freque...

Page 23: ...n Figure 39 The output response to the load step is measured as 150 mV and recovery occurs in less than 5 ms Response to the transient load condition confirms the results of the loop stability analysi...

Page 24: ...Figures 40 through 43 show several images of the board during a continuous load step as described in Figure 1 Images include top and bottom layers at low and high line All images were taken in open ai...

Page 25: ...p onsemi com 25 Figure 42 Thermal Image of the Top of the Board at High Line During a Continuous Load Step Condition Figure 43 Thermal Image of the Bottom of the Board at High Line During a Continuous...

Page 26: ...0 W 48 W converter is designed and built using the flyback topology The converter is implemented using the NCP1219 The average load efficiency is measured above 83 5 over the complete operating range...

Page 27: ...inutes and start the integration cycle 20 Measure VOUT standby using the corresponding multimeter Record the results in Table 5 Verify it is within the limits of Table 4 21 Measure and the integrated...

Page 28: ...ble 4 DESIRED RESULTS Input Voltage IOUT For 115 Vac 60 Hz input 70 mA 7 V VOUT standby 8 V 70 mA PIN 1 W IOUT specified in Table 3 VOUT 24 0 2 V 25 50 75 100 havg 83 5 For 230 Vac 50 Hz input 70 mA 7...

Page 29: ...ication by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as component...

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