NCN5192NGEVB
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12
APPLICATION IDEAS
The NCN5192 takes care of the HART modulation. This
HART signal must then be superimposed on a 4-20 mA
current loop. The NCN5192 simplifies slave implementation
by including an integrated DAC. Below are some possible
implementations of both a master and slave transmitter.
Slave Implementation
A simple slave implementation is shown in Figure 18. The
analog loop current is set by the integrated DAC, and HART
signals are added to this by a resistive summing network.
The DAC is implemented as a sigma-delta modulator, which
means that additional filtering should be implemented. To
explain the operation of this circuit, let us first look at an
example where the DAC is not of a switching topology, such
as shown in Figure 17. As one end of R
6
is tied to local
ground, and current passing through R
7
also passes through
R
6,
it can easily be seen that the voltage at the negative loop
terminal is negative with respect to the local ground.
Resistor R
4
is then chosen so that in steady state their
common terminal is a virtual ground point in the absence of
HART signals, since the negative terminal of the amplifier
is also connected to ground. A similar principle applies
when HART signals are applied. So both amplifier inputs are
regulated to ground.
Figure 17. Simple Slave Implementation
A compensation capacitor C
4
may be required depending
on the operational amplifier used. To avoid offset generated
by bias current in the operational amplifier, a resistor R
3
should be placed on the negative input, and dimensioned to
approach the impedance seen by the positive terminal.
The amplifier will then determine the current flowing
through the loop by changing the base of a transistor in
emitter feedback configuration. The value for R
7
is
determined by the output range V
o,max
of the amplifier used:
R
7, max
+
V
o, max
*
V
BE
20 mA
It is often recommended to take a value as large as
possible, so that noise effects are minimal.
Typically the value of R
6
is chosen equal to R
7
. The
voltage over R
6
and R
7
combined should however be less
than 12 V when the current setting is 20 mA.
Next, the value of R
4
is chosen depending on the most
significant bit of the DAC.
2 V
MSB
R
2
+
20 mA R
6
R
4
When the DAC is not a switching topology, we can now
choose R
1
and C
1
. We have:
500 mV R
2
+
1 mA R
6
Z
Where:
Z
+
Ť
1
sC
1
)
R
1
Ť
In practice, C
1
is chosen sufficiently large so that Z
≈
R
1
.
Because the integrated DAC has a sigma-delta output, a
circuit using the NCP5192 gets a bit more complicated, as
can be seen in Figure 18. We need to filter away high
frequency DAC components, but leave HART signals intact.
A simple RC-filter is not sufficient, since the output
capacitor has low impedance for HART frequencies. We can
do this by replacing the summing resistor R
4
by a T-filter.
This filter has high output impedance due to the output
resistor.
To dimension this filter without too much calculation, we
can treat it as a RC-filter using its first branch. The 3-dB
frequency should be placed just above the DAC bandwidth
(10 Hz).
We get, with R
4
≈
R
5
:
f
3dB
+
1
2
p
C
3
R
4
To dimension the summing resistor of the HART input, we
can no longer assume that the positive input of the amplifier
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