OKIDATA OKIPAGE 20, Service Manual

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Service Manual - OKIPAGE20
Chapter 2 Operation Description
The control board consists of an one chip CPU, a LSI program/font ROMs, four DRAMs, an EEPROM, a
host interface circuit, and a mechanism driving circuit.
(1) One-chip CPU
The one-chip CPU is a custom CPU (32-bit internal bus, 32-bit external bus, 40-MHz clock, that
incorporates and RISC CPU and its peripheral devices, and has the following functions.
Built-in device Function
Chip select controller
Bus controller
DRAM controller
Control of peripheral LSI, ROM, RAM and I/O device
DMA controller Transfer of data from Host I/F to RAM
Serial interface controller Control of RS-232C serial interface
Parallel interface controller Control of Centronics parallel interface
Timer Generation of various control timing
Monitoring of paper running and paper size
Serial I/O Port Control of serial interface between controller and operator panel,
EEPROM Control of a serial interface between controller and
power supply board.
I/O Port Input and output of sensor and motor signals.
Outputting of various control signals
Motor driver controller Control of Main Motor
Compression/extension circuit Compressed frame buffer is produced by compressing the data
of temporary band buffer.
Extension printing operation is executed by extending the data
of compressed frame buffer.
(2) Program and Font ROMs
The program/font ROM's store the HP LJ5 emulation program and various types of font. MASK ROM is
used as the program/font ROM's.
(3) DRAM's
4-Megabyte DRAM (16 Mbit DRAM x 2) is mounted as resident memory to be used for storing
the program and providing various buffers. This DRAM is expandable up to 68 Mbytes by
adding expansion memory (SIMMs). This DRAM provides the areas shown in the following
table.
Memory capacity setting