Oki MSM85C154HVS, User Manual

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MSM80C154S/83C154S/85C154HVS
4
execution from the next address after the stop address where CPU power down mode was
activated.
Each of the quasi-bidirectional ports 1, 2, and 3 can be set independently as high impedance
input ports. And the 10 k
W
pull-up resistance for these input ports can be isolated from the
power supply (V
CC
), leaving only the 100 k W pull-up resistance and thereby enabling the
quasi-bidirectional ports to be driven by devices with low drive capacity. Furthermore, the
outputs of ports, 0, 1, 2, and 3 can be switched to floating status during CPU power down
modes (PD, HPD).
Three built-in 16-bit timer/counters capable of operating in a wide range of modes enable the
CPUs to be used in many different ways. And since timer/counters 0 and 1 can be operated
by external clock during CPU power down modes (PD, HPD) where the oscillator is stopped,
these two counters can also be used in cancelling CPU power down modes.
UART based serial communication can be executed at any baud rate by carry signal from
timer/counter 1 or timer/counter 2.
If an overrun or framing error is generated during data reception, the SERR bit in the I/O
control register is set. And by testing this SERR bit, the accuracy of the data can be checked
quite easily to ensure correct serial communication.
As can be seen, these CPUs are equipped with a very comprehensive range of functions. Also
note that EASE80C51mk
II is available for use as the program development support system
for these CPUs.
Equipped with the MSM85C154E dedicated evachip, EASE80C51mk
II
is capable of pro-
gram area mapping, realtime tracing, generating breaks according to accumulator contents,
and various other functions designed for accurate and efficient support of program develop-
ment of these CPUs.
With this great line-up of functions and with EASE80C51mk
II capable of developing
programs in a very short time, MSM80C154S/MSM83C154S/MSM85C154HVS give a highly
integrated high performance solution.