Table 41. Single oscillator source clock select
(continued)
Functional signals
Reset configuration name
Value (binary)
Options
IFC_OE_B
Default (1)
cfg_eng_use1
On-chip LVDS termination must
NOT be enabled when external
(off-chip) termination are active.
0
On-chip LVDS termination disabled
1
On-chip LVDS termination enabled
IFC_WP_B[0]
cfg_eng_use2
Don't care
Reserved
5.33 DIFF_SYSCLK/DIFF_SYSCLK_B system-level
recommendations
Table 42. DIFF_SYSCLK/DIFF_SYSCLK_B system-level
checklist
Item
Completed
DIFF_SYSCLK/DIFF_SYSCLK_B can be selected to provide primary clock to the chip.
Although it is a Low Voltage Differential Signaling (LVDS) type clock driver but it has AC/DC characteristics
identical to the SerDes reference clock inputs which are High-Speed Current Steering Logic (HCSL)-
compatible. This eases system design as same clock driver can be used to provide the various differential
clock inputs required by the chip
DIFF_SYSCLK
DIFF_SYSCLK_B
100 Ohm
LVDS
RX
Figure 20. LVDS receiver
Interfacing DIFF_SYSCLK/DIFF_SYSCLK_B with other Differential Signalling levels
Connection with HCSL Clock driver
Table continues on the next page...
Interface recommendations
QorIQ LS1046A Design Checklist , Rev. 2, 06/2020
NXP Semiconductors
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